Electronic – No. of comparators in Parallel ADC

I'll give you a hint. Break the inputs into two groups of four. Use a Karnaugh map to give an output when one and only one of four inputs is high. Use another Karnaugh map to create an output that is high when all of the inputs are zero. If you applied 0 through 3 to one of these logic circuits and inputs 4 through 7 to the other logic circuit, can you see how you might combine the outputs of the two logic circuits to give you what you want, at least for four of the inputs?

Now create an exact duplicate of that, but swap the groups of four inputs.

Now you have a big logic circuit with two 1-of-4 logic blocks and two all-0 logic blocks. You can combine the outputs of these blocks to get V.

You can use the comparator to build a Delta Sigma ADC.

You have to disconnect the negative comparator input from ground and connect it to a low pass filtered digital output of your digital logic (FPGA).

EDIT:
The 2nd picture in your post (I think you added later) is exactly what I mentioned above. It represents a Delta Sigma ADC. (So I think I don't need to provide any reference any more. BTW you will find enough references if you search the web with keywors "Delta Sigma converter").

The block diagram, however, shows something that makes me wonder:
there is a LVDS receiver where a I would expect an analog comparator.

A differential receiver is some kind of comparator, but I doubt that it is well suited for this application. For its original purpose as differential receiver just has to be fast but not very exact concerning the differential voltage (offset) and probably it has considerable hysteresis.

A precision comparator would be more appropriate.