bit-errorcommunicationerror correctionparity
How many errors can a transmission system which uses code words with 7 data bits and a single parity bit (Checking for Even parity) detect at the receiving end.
While I am aware of the fact that any odd number of errors can be detected with this kind of a system, what exactly would be the answer? Or is the answer just one?
Ps. I'm not sure if this is the right Stack site to post this question. Do let me know if it isn't.
If your bit-error rate is measurable but not so high that no level of error-correction logic would help, you should either slow down your communications rate by 1% or so, or use the "best" 16 bits of your bus and not bother with the others.
Error correction logic is only useful in cases where the probability of an errors is relatively low and the probability of two errors occurring is far below the probability of one, the probability of three errors occurring is far below that, etc. For a connection between a CPU and an FPGA, either you'll be meeting timing constraints, in which the most probable causes of errors will be things like power-supply glitches (which should be best addressed by power-supply improvements), you'll significantly miss timing constraints (in which case at least some bits of the bus will routinely yield incorrect data), or you'll be right on the edge of meeting timing constraints (in which case increasing timing margins even a little may help enormously).
If you were worried about guarding a parallel-data cable that went between boards, then the primary data to be guarded against would probably be that of a disrupted communication (e.g. one that was happening while a connector was unplugged) being perceived as legitimate. Unless very-short-turnaround transactions are required (as might be the case here), such things are best guarded against by performing a CRC or other validation code on all the words of a longer transmission. Appending a two-word (32-bit) CRC to a 64-word transmission would less overhead than adding a parity bit to each word, but would be far more likely to detect transmission errors.
You wanna use IC 7486 quad xor gate.It has 4 xor gate in it.the pin diagram is like the first image.
Best Answer
I'm not sure exactly what you're asking. If you fail a parity check, you are assured that there is at least one bit of the 8 in error (it may be the parity bit). There may be 3, but you have no way of distinguishing the two results. Further, if you have an even number of errors, they will result in no detected error at all.
No matter what, you have no indication which bit is in error, so parity is useless for any error correction.
Parity is generally used in systems which are reliable enough that the probability of having more than one error in N bits (N=8 in this example) is considered negligible.