cmosinvertersymbol [~]
During study , I am encountered with this two Inverter symbols . 
Sometimes this two symbols are usedn in same logic circuit. Though they are working as inverter, I'm guessing there must be some charecteristic differences indicated by this two symbols.Or there is no logic to use two different symbols in same circuit.
Is this symbols indicated different kind of inverters or some different physical properties ?
Some people claim that certain loads "may" not work as well, or "may" be damaged, with anything other than a pure sine wave.
Since the power coming out of my wall sockets is significantly different from a pure sinewave, I suspect these sincere and well-meaning people are merely repeating propaganda from the manufacturer of a pure sinewave inverter, much like people repeat urban legends.
There is only one kind of device that I know doesn't work as well with a non-sine-wave inverter: devices that use a "capacitive power supply" -- see How efficient is a capacitive power supply? for details.
Since a "capacitive power supply" has a power factor near 0, it is questionable whether any "capacitive power supply" meets EU-mandated power factor laws, such as EN61000-3-2.
I suspect that all products -- as long as they were designed after EU-mandated power factor laws went into effect -- should work just as well on "modified sine wave" as with "pure sine wave" inverters.
Of course, I can't possibly know about every product ever designed -- if there is any specific product (that was designed after those EU-mandated power factor laws went into effect) that can't work or doesn't work as well with "modified sine wave" power, I would be interested. If anyone can explain why it doesn't work, in enough detail that I can try to avoid that kind of failure, I would be fascinated and grateful.
If I understood your intent correctly, you are trying to measure leakage currents using DC simulation on the following circuit:
The code I got (omitting all the usual setups) is:
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_1 IC Gnd Gnd NMOS W=250n L=250n AS=225f PS=2.3u AD=225f PD=2.3u
MNMOS_2 IC N_1 Gnd Gnd NMOS W=250n L=250n AS=225f PS=2.3u AD=225f PD=2.3u
MPMOS_1 N_1 IC Vdd Vdd PMOS W=500n L=250n AS=450f PS=2.8u AD=450f PD=2.8u
MPMOS_2 IC N_1 Vdd Vdd PMOS W=500n L=250n AS=450f PS=2.8u AD=450f PD=2.8u
VVdd Vdd Gnd DC 2.5
********* Simulation Settings - Analysis section *********
.dc lin vVdd 0 2.5 100m
********* Simulation Settings - Additional SPICE commands *********
.ic v(IC)=0
.print DC gate_leak<A>='(abs(i2(mNMOS_1))+abs(i2(mNMOS_2))+abs(i2(mPMOS_1))+abs(i2(mPMOS_2)))/4'
.print DC subth_leak<A>='(abs(i3(mPMOS_1))+abs(i3(mPMOS_2)))/2'
.end
Note the usage of abs() function - it is required because the currents might have different signs.
The syntax of the printing command is:
i<#terminal>(<device_type><name>)
In the above example:
And the resulting traces:
You can see that the model I used either does not model gate leakages at all, or the value is exceedingly small (I guess the former is true). Subthreshold leakage, on the other hand, seems to be taken into account. Anyway, you said that your models are accurate, therefore it should not be an issue for you.
The above information will help you to get the results you want, but I think that these results won't be too accurate. In fact, for subthreshold currents they will be very inaccurate. The reason for this inaccuracy is that subthreshold currents have exponential dependence on Gate-to-Source bias. In DC simulation this bias will be constant for each transistor. In real applications, there is always some noise which affects the Gate-to-Source bias.
One way to slightly improve the results will be to add some "noise" voltage source in series to each inverter's input. If you sweep the value of this noise you'll be able to get a feeling on how the leakage currents can be affected by noise. However, for approximations that are any good at all you'll have to perform transient analysis and add noise voltage sources which approximate the real noise you'd expect to be present in your system.
If this task is not just educational, but these measurement are going to be taken into account during development of a real hardware, you'll have to run Monte-Carlo analysis to check the values of leakage currents for a whole range of operating conditions.
Hope this helps.
Best Answer
No, there's no difference in performance between these devices.
The lower one is the one that's more commonly used.
The upper one might be used, for example, if the input comes from a NOR or NAND gate and the person drawing the circuit wants to emphasize that this inverter is intended to turn that into an OR or AND gate (by the principle of combining bubbles).