Electronic – Opamp demonstrates slew rate much lower than specified in datasheet

You have wildly complicated your circuit, assuming your symbols mean what the schematic indicates.

First, an instrumentation amp would look like

^{simulate this circuit – Schematic created using CircuitLab}

You show the upper amplifier, which produces OutInv, as being connected to the same ground as R3 and R9. Under these circumstances, OutInv is forced to ground (plus the input offset of the op amp), so you could profitably get rid of the op amp. Furthermore, a gain of 100 is perfectly reasonable from a single op amp, so you could do the whole thing with 1 op amp, as George Herold suggested. A simple version would be

^{simulate this circuit}

This will have a nominal gain of 101. Since an LM358 has a maximum offset voltage of 7 mV, you could have an offset error of 0.7 volts.

Let's assume, though, that the two input grounds are instead a separate ground, isolated from the output ground by some common-mode voltage. In this case, you have connected the upper op amp incorrectly. R1 should be connected to the - input of both amps. However, if you do this, you'll have gain of about 220, rather than 100. The equation for gain for an instrumentation amplifier (assuming R2 equals R3, R4 equals R5, and R6 = R7) is$$G=(1+\frac{2R_2}{R_1})\frac{R_6}{R_5}$$ Alternatively, depending on the output impedance of V1, you could simply use a single op amp set up as a difference amplifier with a gain of 100. You've shown the V1 as a voltage source, so this seems perfectly reasonable.

If you're worried about a stable output, I assume you're worried about noise from the input. This is best handled with an RC filter between V1 and the input.

Does this effect depend on anything else than the JFET/BJT input stage?

Slewing can happen in any stage of an OpAmp, it can happen in the input stage, the output stage and any of the intermediary stages. It occurs whenever a capacitor is driven by a fixed current source. For a given configuration one stage sets the limit and determines the slew-rate often this is in fact the input stage.

A typical input stage consists of a differential pair with a tail current source. In equilibrium the current of the tail current source splits equally and when driven hard on transistor takes the whole current. The required voltage to turn one of the transistors (almost) off determines the onset of slewing. It's a fixed voltage for BJTs and a variable voltage for FETs.

If slewing happens in the output stage and the output stage is not symmetrical (e.g. class A) it is possible to have different slew-rates for falling and rising edges.

Are there input stages where an even lower differential input voltage leads to the maximum slew rate? Perhaps some sort of hybrid?

I don't know of any off-the-shelf devices that do this, but certainly there are adaptively biased OpAmps that increase the current through the input stage to improve the slewing behavior.

Even if there are only two types, do different op-amps of the same type (say, BJT) have different levels?

BJTs have a fixed level, unless emitter degeneration is used and FETs can have different levels.