I was trying to design a circuit after seeing this question. I know I used too much components than I should designing a circuit with this purpose. And sorry about the messiness of the schematic.
This circuit compares V1 and V2 and if V2>V1 than it outputs V2. If V1>V2, it outputs V1. I am going to combine U2 and U3's outputs later on. However I don't understand why this circuit behaves abnormally.
Even if the Q2's base shown to have about 20mV, Vbe of Q2 is negative, and V+ supply pin of U3 is 2.42V. Output of U1 is 8.39V and collector of Q3 is about 20mV. Output of U2 is 5V, where the output of U3 is 1.57V.
Why is this odd behavior?
Here is the LTspice file.