Electronic – Open collector / drain question

That's right, open collector is BJT, open drain (C)MOS. In logic circuits where currents are low the saturation voltage of the BJT may be a bit higher than the voltage drop due to \$R_{DS(ON)}\$ for the FET, but it still will be much lower than the maximum voltage for a logic low.

Exception: you can't use a TTL open collector output as a level shifter to interface with very low voltage CMOS. This inverter can operate on a Vcc as low as 0.8 V, and the datasheet gives a maximum low level of 0.25 Vcc, that's 0.2 V. An open collector will have a voltage drop higher than that. (This device even specifies a maximum low level input voltage of 0 V, which is simply impossible.)

note
Apart from wired-ORing (think I2C) open drain/collector is often used to control something operating at a different voltage than the logic, often a higher voltage. With some low-voltage logic families this no longer possible, since the FETs will not tolerate the high voltage and for that reason some families will have clamping diodes built-in to protect the output FETs.

There really isn't an issue with that. Open drain and open-collector are essentially the same in this application.

Two things to watch out for:

1. Make sure you get your polarities right and that you need an OR gate and not a NOR gate because the open-collector/open-drain style often invert your signal. If the output of either opamp is high, then the output of that IC will be pulled low, and vice versa.

2. Just make sure each IC can sink (Vcc/R1)+(Vcc/R2). This will be the worst case current if one output is low, and the other is high.

Picture for reference.