I'm a new Eagle user and I created an SOIC part with a small heat pad in the middle. The pad is on the bottom and at the top copper layers. The bottom pad is purely for soldering convenience sake. Its easy to solder the pad by heating the bottom pad with your soldering iron.
The board has 2 layers and the bottom one is all GND. I've attached an image here.
The manufacturer says that I should extend the heat pad beyond the IC and put some vias so that heat is transferred to a larger plane. I've put these vias and named them GND but I keep getting an "Overlap" error. Why is this?
Also all the copper pours are created with zero widths because it gave me better control over the fill and now I get "Width errors". How do I resolve these?
Best Answer
There is a DRC option (Clearence -> Same Signals -> SMD-VIA) that checks the distance between VIAs and SMD pads, even if they connect to the same signal. This is probably the reason why you get the OVERLAP error.
As a workaround you could just set this restriction to 0. But you should consider placing the VIAs within your package design, since the DRC will ignore the minimum distance rule in that case.