Electronic – overshoot and undershoot on 3 volt pulse

1. Decoupling capacitors are known in circuits' power supplies, where they serve to keep the supply voltage clean of (high frequency) noise. But I have the impression that here removing DC content of your signal is meant, by means of a series capacitor, like C24 does for the input. Which, depending on your point of view (DC or AC) can be called a coupling capacitor. But there's no capacitor that does this on your output. The value of C23 is also suspectively low. The cutoff frequency with resistors R23 and R24 is 12 kHz, which is useless, because that will be about the frequency range of the cassette anyway. I'd rather expect 5 kHz here. Also the text speaks of the MIC input, but for that the output level is too high. The schematic mentions the line input.

2. The CA3140 is no good. Its minimum operating voltage is 4 V, and at 5 V the output high doesn't go higher than 3 V, so for 4 V supply that may be as low as 2 V, and that may not be enough for the Spartan. Use a Rail-To-Rail opamp instead, or even better a comparator.

edit re your new questions

1. Polarity is OK, since it doesn't matter :-). You have an AC signal going above and below ground. Like you've drawn it the positive half cycles will make the output go to Vcc, the negative to ground. If you switch the inputs you'll have the reverse, but both signals will look the same.

2. Yes.

3. I would ignore it. It doesn't seem to have a function other than loading the output, and besides, if you dot it out you're asking for being ignored :-).

Important thing about R1: this should go to Vcc, your 3.3 V, not in series with the output. The open-drain output means that there's only a FET switching the output to ground, so it can only make it low, not high. The pull-up resistor will make the output high when the FET is off.

What you want to do is called a Numerically Controlled "Oscillator", or NCO. It works like this...

Create a counter that can increment by values other than 1. The inputs to this counter are the master clock, and a value to count by (din). For each clock edge, count <= count + din. The number of bits in din is the same as the number of bits in the counter. The actual count value can be used for many useful things, but what you want to do is super simple.

You want to detect every time the counter rolls over, and output a pulse to your motor when that happens. Do this by taking the most significant bit of the counter and running it through a single flip-flop to delay it by one clock. Now you have two signals that I'll call MSB, and MSB_Previous. You know if the counter has rolled over because MSB=0 and MSB_Prev=1. When that condition is true, send a pulse to the motor.

To set the pulse frequency, the formula is this: pulse_rate = main_clk_freq * inc_value/2^n_bits

Where inc_value is the value that the counter is being incremented by and n_bits is the number of bits in the counter.

An important thing to note is that adding bits to the counter does not change the range of the output frequency-- that is always 0 Hz to half of main_clk_freq. But it does change the accuracy that you can generate the desired frequency. Odds are high that you won't need 32-bits for this counter, and that maybe just 10 to 16 bits will be enough.

This method of generating pulses is nice because it is super easy, the logic is small and fast, and it can often generate frequencies more accurately and with better flexibility than the type of counter+comparator design that you have in your question.

The reason why the logic is smaller is not only because you can get by with a smaller counter, but you do not have to compare the entire output of the counter. You only need the top bit. Also, comparing two large numbers in an FPGA usually requires a lot of LUTs. Comparing two 32-bit numbers would require 21 4-Input LUTs and 3 logic levels, where as the NCO design requires 1 LUT, 2 Flip-Flops, and only 1 logic level. (I'm ignoring the counter, since it is basically the same for both designs.) The NCO approach is much smaller, much faster, much simpler, and yields better results.

Update: An alternative approach to making the rollover detector is to simply send out the MSB of the counter to the motor. If you do this, the signal going to the motor will always be a 50/50 duty cycle. Choosing the best approach depends on what kind of pulse your motor needs.

Update: Here is a VHDL code snippet for doing the NCO.

signal count :std_logic_vector (15 downto 0) := (others=>'0);
signal inc   :std_logic_vector (15 downto 0) := (others=>'0);
signal pulse :std_logic := '0';

. . .

process (clk)
begin
  if rising_edge(clk) then
    count <= count + inc;
  end if;
end process;

pulse <= count(count'high);