pspice
I created the following circuit in Pspice:
In the simulation profile I made sure that all flip-flops are initialized to 0. When I run this simulation I get the following error message:
I just can't figure out what is the problem… can you help me with that?
thanks a lot…
I don't know which version of PSpice are you using. But after adding TR and TF a small value, it works. Usually a 1 picosecond rise/fall time is extremely small with regard to the simulation time, so it closely approximates the ideal step function. Set them to 0 may cause convergence problems in some transient analysis simulations.
Try adding a ground node (see left side):
simulate this circuit – Schematic created using CircuitLab
The netlist would be something like:
R1 N2 0 5k
C1 N2 0 22µ
D1 N1 N2 1N914
V1 N1 0 SINE(0 3 1000)
Just note the use of 0 for ground.
EDIT: Okay. So you are using a ground. That's good. There is often a parameter to let you arbitrarily connect every node to ground via a high impedance value (GMIN.) But I don't know how you'd access it in your simulator. So lacking that, try the schematic on the right side, now, as shown above.
Best Answer
My opinion is as follows:
Your circuit works as an asynchronous binary counter, changing its count at every falling edge of the input clock (stimulus DSTM1), starting at 0,0,0 state (Q3,Q2,Q1 according to my schematic_diagram).
As soon as the count reaches 1,1,1, i.e. after ~3.5us, it comes to a "problem" because the inverted output Q3bar=L (signal clr) would immediately clear all the three flip-flops, and therefore, it tries to set back to Q3bar=H also itself.
The time of the generated impulse is too short to clear the flip-flops. The waveform diagram shows that the value of Q3 and 'clr' (Q3bar) is due to it undefined from that time on. That's why at the next counting edge at 4.5us the value of Q1 cannot be determined (see the waveform diagram - the red waveform Q1) - because of the 'PERSISTENT ERROR at "CLEAR" input of X_U1A' (your error message). When you prolong the clearing signal duration, it will clear the flip-flops properly and the problem disappears - see the modified schematic diagram, where the clr signal is hold at L level for one half of the clock period.