Electronic – Photocurrent in photodiode smaller than expected

I'll edit this answer severely as a general comment:

Photodiodes may be operated either forward or reverse biased.

• Forward biased gives most output.

• Reverse biased gives most speed. and is noisier.
  In this mode Vsupply needs to be < Vreversebreakdown - hopefully in the data sheet.

Reverse biased mode is most usually used.

The Sharp BS120 is optimised for 560 nM operation. It specifies Vreverse_abs_max as 10 volts and has curves all the way up (or down) to -10V.

Wikipedia says

In "forward biased" mode the diode is usually operated with NO added bias and is used as a voltage source.

For a silicon diode with Vforwards = Vf = 0.6V . Say you want 5 mA current and are using a 5V supply then

I = V / R = = (Vsupply - Vdiode) / R = (5-0.6) / 0.005 = 880 ohms Say 1000 Ohms (which gives a notional 4.4 mA)

For 1 mA you'd use (5-0.6)/0.001 = 4400 Ohms

This is a commonly misunderstood misused set of terminologies.

First off these are not PIN Photodiodes - which stands for P - Intrinsic- N. These have large depletion regions for higher internal QE (Quantum Efficiency) and faster response. You can't make an array with this design though.

Pinning, refers to fermi-level pinning or pinning to a certain voltage level. Or also the forcing or prevention of the fermi-level/voltage from moving in energy space.

You can get surface state pinning from the dangling Si/SiO2 bonds providing trapping centers. A buried PD (Photodiode) has a shallow implant that forces the charge carriers away from these surface traps. The Si/SiO2 surface contributes to increased leakage (dark current) and noise (particularly 1/f noise from trapping/de-trapping). So confusingly a buried PD avoids pinning of the fermi-level at the surface.

A pinned PD is by necessity a buried PD, but not all buried PD's are pinned. The first Pinned PD was invented by Hagiwara at Sony and is used in ILT CCD PD's, these same PD's and the principles behind this complete transfer of charge are used in most CMOS imagers built today.

A pinned PD is designed to have the collection region deplete out when reset. AS the PD depletes it becomes disconnected from the readout circuit and if designed properly will drain all charge out of the collection region (accomplishing complete charge transfer). An interesting side effect is that the capacitance of the PD drops to effectively zero and therefore the KTC noise \$ q_n = sqrt(KTC) \$ also goes to zero. When you design the depletion of the PD to deplete at a certain voltage you are pinning that PD to that voltage. That is where the term comes from.

I've edited this Answer to acknowledge Hagiwara-san's contribution. It has long been incorrectly attributed to Teranishi and to Fossum (in CMOS image sensors)