Electronic – Pi Filter Grounding for RF sampling ADC

I will start with a shift of terminology here -- instead of "grounds", we have "returns" -- namely a power return and a signal return. The power return is the easy case -- it should be a star topology with the star point at the power supply output, tying to the signal returns of each board at a single point in turn, and also to the chassis ground at a single point.

Now, we have the RF and processing boards to deal with. Each board has a signal return, which is handled through a ground grid at a minimum, if not a full ground plane. This return is contiguous, even on the RF board, and also is interconnected between the two boards alongside the digital signals passing between them.

The digital board can be laid out freely, provided the loops are kept small. This is not true for the RF board, though, which needs to have a layout that is strictly partitioned between analog nets and digital nets -- there should be an "analog area" on the board that has only analog signals, and a "digital area" on the board that has only digital signals. The return currents will then proceed to stay with the signals they are paired with, thus keeping them separated without the need to do any ground plane splitting.

Finally, connector shields need to be returned to the chassis ground by the shortest path possible, and there also needs to be a "bridge" between the chassis (I/O) ground and the signal return located with the I/O signals going to the outside world. (ESD/EMI protection devices, as well, return to the chassis aka I/O ground.)

For more information on this topic, I recommend reading Henry Ott's fabulous book, Electromagnetic Compatibility Engineering, and in particular, Chapters 16 and 17 on circuit board layout.

The problem is that eagle does not know which polygon to fill first. For some reason, it doesn't care and "merges" both.

The correct way is this:

1. Draw both polygons
2. Assign different net names to them
3. Assign different ranks to them (e.g. in their properties). Polygons with low rank will now be drawn first.

Here is an example with two overlapping L-shaped polygons:

Polygons before ratsnest:

Though different net names are assigned, the polygons are fused. At least, the design rule check will complain:

Setting upper left polygon to rank 1, lower right to 2, and applying ratsnest. The upper left polygon is drawn first, the lower left takes what's left:

Changing upper lefts rank to 3, the lower right polygon now is drawn first: