No, don't disable the digital inputs when using the pin in digital mode. The digital input circuit doesn't really consume power as long as the pin voltage is solidly high or solidly low. You don't save anything by turning it off, and it might cause trouble.
All pins that can be analog inputs wake up that way because it is most tolerant of the external circuit. If a pin is held near the middle of its voltage range, then the digital input circuit in the PIC could draw unnecessary power and possibly even oscillate. So the PIC starts out in the most tolerant mode and the firmware then switches specific pins to other modes as only it knows how the micro is being used.
I have found over the years that except in speed-critical or multi-master applications, it's actually easier to bit-bang an I2C master than to try to use the I2C facilities built into many chips.
Note that if a device uses clock stretching, any time you release SCK, you must wait for it to actually go high. For simplicity, such delays are omitted from the following descriptions, but should be included if appropriate in your "release_SCK()" routine.
To start an I2C transaction, release SCK (if it isn't already) and, if the data line is low, assert SCK (drive it low), release SDA (if it isn't already), and release the SCK. Repeat this process up to nine times until SDA is high. If SDA is still low after nine repetitions, the bus is unusable.
To output each byte (including the address byte), assert SDA, and then for each bit repeat the sequence (assert SCK; set SDA high or low to match next bit of data; release SCK) eight times. After the last bit, assert SCK, release SDA, and release SCK. If SDA is low, a slave is acknowledging; if SDA is high, no slave is acknowledging and the transaction should be aborted.
When all output is complete, assert SCK, then SDA, and then release SCK, then SDA.
To input each byte, assert SDA, then release SCK if it isn't already (it will be for the first byte, but not others). Then reassert SCK, release SDA, and repeat the sequence (release SCK, read data bit, assert SCK) eight times. Note that at the end of this sequence, unlike when outputting a byte, SCK will be left asserted.
When all input is complete, release SDA (it should already already be released) and SCK.
Note that because the clock is left asserted after inputting each byte, it's not necessary to specify whether the byte should be ack'ed or nak'ed. If you read another byte, the last byte read will be nak'ed. If you terminate the read, it will be nak'ed.
Start; send address; write one byte, finish
SCK - -__-__-__-__-__-__-__-__-__-- -__-__-__-__-__-__-__-__-__--- -__--
SDA(M) - __777666555444333222111___--- --777666555444333222111000---- --__-
SDA(S) - -------------------------??AA A------------------------??AAA A----
Start; send address; read two bytes; finish
SCK - -__-__-__-__-__-__-__-__-__--- -__--_--_--_--_--_--_--_--__ -__--_--_--_--_--_--_--_--__ _-
SDA(M) - __777666555444333222111------- __-------------------------- __-------------------------- --
SDA(S) - -------------------------??AAA A??77?66?55?44?33?22?11?00?? -??77?66?55?44?33?22?11?00?? ?-
Best Answer
The idea behind this is the following:
Setting the TRIS bit (making it
1
) will make the corresponding pin an input.A typical extract from a PIC datasheet:
That the pin is in high impedance mode, means (among other things) that the pin is not driven by the chip itself. Therefore, it takes any state that is defined by the external circuit (the circuit around the PIC).
The 1-wire bus uses pull-up resistors. You can see that on the wikipedia article:
As you can see, the default state is high. That means that the bus uses a pull-up resistor to make it's default state high.
That's also written on the wikipedia: