Electronic – PIC18F97J60 Ethernet performance

In principle this is good candidate for FPGA based design. Regarding your requirements:

ad 1. The FPGA most likely will be more expensive, by how much that depends on the device you choose. At first glance smallest Spartan 3 from Xilinx (XC3S50AN) will be more then enough for this task (~10£ from Farnell). I think you can assume this is upper boundary for the cost (it has 56kB RAM inside, so it is more then you need). You may find cheaper device either from Xilinx offering or their competitors Altera and Lattice.

ad 2. The package is the tough issue, I did not saw FPGA with smaller footprint either. However maybe you can use CPLD device (for sake of argument the CPLDs are small FPGAs) which may be in smaller package (PLCC or QFN). On plus side they will be cheaper (even single $) on negative side most likely will not have RAM inside. With CPLD probably you would need external SRAM chip.

ad 3. FPGAs and CPLD current consumption is highly dependent on the programmed design. However there is good chance that FPGA and especially CPLD design would consume less than your current solution.

ad 4. FPGA do have that kind of memory inside, CPLD most certainly not. This may be solved by external sram chip (or two). For example:

|SRAM 1| <--> |CPLD| <--> |uC|
|SRAM 2| <-->

In such arrangement while the uC is writing to SRAM 1, the CPLD will be displaying data from SRAM 2. The CPLD should be able to handle both task simultaneously.

Of course you can solve this in other ways too:
1) use faster uController (ARM for example)
2) use device with some programmable fabric and uC inside (for example FPSLIC from Atmel, however I have never used such devices and I know very little about those)

Standard disclaimer -> as designs are open problems, with many constrains and possible solutions whatever I wrote above may not be true for your case. I believe it is worth checking those option, though.

As far as I know there are no 32-bit versions of the PIC18F97J60 chip. I believe Luminary Micro (now TI) did have one, but I am not sure if they are still available (I think I read somewhere they went EOL).

The ENC424J600/624J600 chips provide MAC+PHY in 1 chip, and communicate via SPI or parallel interface to any microcontroller. However you need to haul all of the frame data over this SPI/parallel interface. The SPI interface can only run at 20MHz or so, so the SRAM buffer will overflow at medium to high throughput. It's nice the chip can communicate on 100Mbps networks, but it cannot sustain that data rate. To avoid this you could run the interface via parallel (that can transfer up to 80/160Mbps between MCU and Ethernet controller), but that will involve a dozen or more connections between the chips.

The LAN9220 chip looks very similar to the ENC624J600, but only supports parallel.

I would suggest looking into the "MII/RMII Phy chips" if you can specify one of the higher-end PIC32MX6xx or 7xx series chips (or alternative ARM part). They include the MAC controller inside the microcontroller, with frame buffers allocated inside your MCU RAM. You only need a cheap external PHY chip, which basically translates the MAC data to compliant Ethernet signals. Best of all, RMII/MII is not exclusive to Microchip. Many ARM microcontrollers support RMII/MII ethernet interfaces as well. The biggest advantage is that the major data movements are all handled by hardware or DMA. Once the software/ethernet stack is prompted about a new packet, it's already in the MCU RAM ready to be processed. This yields very decent/good throughput and the lowest latency of the bunch.

MII is basically two seperate 4-bit data busses running at 25MHz. You just tie them together to the MCU and off you go. RMII halves the 4-bit bus to 2-bit (less signals), but runs at 50MHz.