For a PLL in short,
1) What controls loop bandwidth?
2) What impact does it have on output phase noise/jitter?
3) What impact does loop bandwidth have on PLL lock time?
I am trying to find answers to these questions, could you help?
Electronic – PLL loop bandwidth, lock time and jitter
pll
Related Topic
- Electrical – Phase Locked Loop: Confusion in Lock Range
- Electronic – Help to translate jitter design constraint in a frequency synthesizer design with 4046 and 4017 ICs
- Electronic – PCIe Gen2 PLL lock issue
- Electronic – Choosing PLL Loop Filter Bandwidth and Phase Margin for Frequency Ramp Generation
- Electronic – Accommodating Gain Elements in PLL Loop
Best Answer
This gain includes the phase detector gain, any dividers in the loop, and the VCO tuning constant. If we break the loop at the VCO tuning input, we are controlling the frequency, but measuring the phase. This gives us a pure integrator. The loop has an irreducible 90 degrees phase shift to go with its falling frequency response.
The reference input frequency has phase noise and jitter. The VCO in the PLL has phase noise and jitter. The output signal comprises mostly the reference jitter below the loop bandwidth, and mostly the VCO jitter above the loop bandwidth.
If the output has too much of the VCO noise in it below the loop bandwidth, then we can increase its rejection by adding integrators below the loop bandwidth, broken back at the loop bandwidth for stability.
If the output has too much of the reference noise in it above the loop bandwidth, we can improve the rejection by adding low pass filters above the loop bandwidth, far enough above for minimal additional phase shift at the loop bandwidth.
Some PLL's actually adjust the loop bandwidth on the fly. When the PLL has not locked, the bandwidth is high and lock time is improved. But after locking, the bandwidth is reduced to reduce the reference jitter and noise.