In order to reduce back-EMI of a Buck converter a LC input filter is to placed in front of the converter. To limit the inrush current when those caps are charged I consider to use a PMOS with a RC filter at its gate.
The following schematic shows the whole input stage including inrush current limiter (M1), reverse voltage protection (M2) and fuse.
During simulation I noticed that placing a capacitor from gate to source (C5) is much more effective in limiting inrush current than placing it from gate to drain (C4). This contradicts sources on the net like here that show the capacitor from gate to drain. Is the effect I see only in my simulation or is this due to the fact that I don't actively drive my PMOS but effectively tie it's gate to ground?