Capacitors in series are like resistors in parallel, to get the total capacitance add the reciprocals, then take the reciprocal of the result.
For example, if we have 20pF, 10pF, and 5pF caps, the total capacitance would be:
1 / ((1 / 20pF) + (1 / 10pF) + (1 / 5pF)) = 2.857pF
For two capacitors you can use the (C1 * C2) / (C1 + C2) but this won't work for 3 or more.
20pF 10pF 5pF
Connect here -> -||---||---||- <- and here
2.857pF
Equivalent to: ------||------
Note that putting multiple caps in series probably won;t work very well at such a low value (there will be extra unwanted inductance which will lower the resonant frequency)
2.2pF is actually a very common value, for example Farnell has 46 options under RF caps and 94 options under ceramic caps. I advise picking one of these.
When
- the voltage produced by the uC is sufficient
- the switching time (resulting from the - limited - drive capability, maybe further limited by a series resistor, and the effective (!) gate capacitance) is acceptable
- there is no danger of 'backdrive' from the switching in the mosfet back to the gate to the uC (this can be a reason to include a gate series resistor)
When you are switching a 20mA LED or a 100mA relais using a TO92 logic-level mosfet I would drive the gate directly without hesitation (but I would check whether the gate voltage is sufficient) . When PWMming 10A motor I would not dream of doing so. In between there is of course a gray area, where careful consideration (and some smoking experiments) might save you a mosfet driver chip.
(edit - add "using a TXB0108 as fast mosfet driver")
The TXB0108 is a wonderful chip, but it drives its outputs in a very special way: a short pulse of relatively low impedance (50..100 ohm), then sustained by a relatively high impedance (4k). I could not find the duration of the pulse in the datasheet.
Your mosfet must have an low enough effective gate capacitance that it is sufficiently charged by the pulse. As ballpark value you could use the 70pF mentioned in the TXB0108 datahseet (minus PC stray capacitance, etc.).
The switching delays of the TXB0108 are up to ~ 10 ns with 15 pF load. This does not make me feel comfortable about reaching 100 ns with 70 pF.
The allowed voltage on a TXB0108 pin is 0.5 .. 6.5 V: there is margin beyond the supply range, with clamp currents of 50 mA. That might well mean that the chip is reasonably protected from latch-up and other unwanted effects that could be caused by backdriving. But note that this is in the infamous 'absolute maxima' section, NOT in the normal operations.
Management summary: the TXB0108 datasheet does not provide sufficient details, ballpark spec for the mosfet is < 50 pF effective gate capacitance, 100 ns might be achievable, but experiments will be needed to verify the design. Backdriving might not be a problem (specs look much better than an average uC pin), so the series resistor might not be needed, but again: insufficient data.
Best Answer
The power dissipation of a CMOS chip can be considered as the sum of the static power dissipation (leakage current times supply voltage) and dynamic power dissipation.
Dynamic power dissipation in turn consists of the power dissipation related to switching internal nodes and drivers and the power dissipation related to switching external load capacitance. Every time you charge and discharge (one cycle) a capacitor energy is consumed E = \$ \frac {C V^2}{2}\$, so if the frequency is \$f_0\$ then the dynamic power consumption is P = \$ \frac {f_0 C V^2}{2}\$ (per node). Half the energy transferred is lost as heat on each edge.
In the case of the 74HC595, the internal dynamic power consumption is then
\$ P_{dyn int} = \frac {f_0 C_{PD} V^2}{2}\$ (specified in the datasheet as with all bits switching)
To get the total power dissipation you would add the static power dissipation, the above internal dynamic power dissipation and the dissipation due to load capacitance on each output
(similarly it will be \$ \frac {f_0 C_L V^2}{2}\$ for each output).
Although the static power dissipation is mostly related to the power supply voltage, note that the dynamic power dissipation is proportional to the square of the supply voltage, so a reduction in supply voltage from 5V to 1.8V (2.8:1) will reduce the dynamic power consumption by a factor of 7.7:1.
So, if you're a board-level designer and are interested in low power, you can use the slowest frequency and (especially) the lowest supply voltage possible. If you're a chip designer you want the parts to work at very low supply voltages (which means they can't handle relatively high voltages generally). As a side effect, such transistors tend to leak more so the static power dissipation increases even for transistors that are not switching at all.