Some said create vias to the ground planes. But should I do that for every pin?
Through-hole pads don't need another via --- they already extend through the board to all layers.
For SMT, one via per pad is a starting point. Each component probably has its own current draw so you want to have enough vias to accomodate that. But you might find cases where it's not needed. For example, a bypass capacitor next and the power pin for an IC placed near each other probably can share one via.
Because sometimes when I create via to each component then route their connection on the ground plane, the net line doesn't disappear all the time.
Generally I hide the ratsnest lines for power and ground pins during the initial part of the design. Then they don't clutter things up while you're routing the signals. Once signals are routed, turn the power and ground net ratsnest back on. As you connect each pad to the planes, you should see one netline disappear. It might not be the one you expect, but by the time you connect all the pads to the planes, they should all be gone.
Then other sources say create polygon pours after the connection is done.
Altium distinguishes polygon pours from plane layers.
Polygons are positive features on positive (signal) layers, that fill large (or small) areas.
Plane layers are negative layers where copper is present on the entire surface, except where features are defined. If you make a polygon on a plane layer, you will produce a region with no copper, not a region with copper.
Making polygons last is mainly a convenience: Redrawing polygons can take a long time, and you don't want to be waiting for it to happen all the time during your design, so you draw your polygons last to avoid that inconvenience during most of the design process.
To mass-hide all component designators:
- Shift+F, then click on a component designator
- It says Object Kind, Text, Same. Change the box String Type, Designator from "Any" to "Same"
- Click OK
- All component designators are selected.
- In the PCB Inspector, click Hide->True
- If you have some hidden already, this will Unhide all
- Click again to hide all
When you want to unhide them all, go into a component dialog and uncheck Hide in the Designator area. This will give you something to click on for the Shift+F operation.
Best Answer
This answer is twofold, answering these questions:
1. Can you do it?
You most probably can. In the Clearance Rules you can use the keyword "IsStitchingVia", or the parameter line "IsStitchingVia and InNet('{yourNetName}')" for a specific net for the first object and for the second object you can use "InLayer('{yourLayerName}')" and all kinds of specific keywords to find component labels.
But I have never tested whether this works with Silkscreen specifically, since: See 2.
2. Should you want to do it?
No. You should want to keep the stitching as perfect as your design allows, because if you have a need for stitching, you have a need for it to be good and as complete as possible.
Want to make sure your designators are still readable over a via in your stitch? You have them filled and tented. Or very tiny and tented will also often fill them with solder mask automatically - whether filled and tented or tiny and tented is cheaper depends on your fab, but it's extremely likely tiny and tented is cheaper these days.
Appendix: How to tent stitched vias
To fully tent your vias, in the "Add Stitching to Net" menu click the check-marks in front of "Force Complete tenting on Top" and "Force Complete tenting on Bottom". In Version 15 that's lower right, I seem to remember the same for 14, for 16 I don't know as I'm in a critical design and can't risk an update right now.
How to get the vias neatly filled is, as far as I know, asking the Fab what parameter to set and how, but to be honest, last design with Altium I had filled vias my colleague did that, making the last time I specifically requested them myself 2007, so I forgot. (It's possible he just phoned them to ask how small a via should be to guarantee it gets filled with solder mask when tented, to be honest)