Electronic – Problem with glue logic/memory decoding on a 6502 project

Verilog can handle the chip select approach - the high impedance state is called Z.

However, whether synthesis can handle it depends on whether whatever you're trying to synthesize to has the necessary tristate drivers available, and whether the synthesis program knows how to use them.

Disconnecting inputs from the bus isn't necessary; just the outputs.

It worked this way back when I specialized in ASIC and FPGA logic simulation using Verilog.

Your mapping the address bus method isn't clear enough that I can say much on that.

I put on my teacher/professor hat.

• your text mentions an 8Kb RAM, your diagram shows 16Kb.

• your ROM has 32 locations, hence it needs more than the 2 address lines you connect to it. Even if you intend to connect some lines to a fixed value, you should how that.

• the question explicitly asks for the PROM content, which you don't give. Yes, it is a 32x8 table of 1's and 0's, but the point is which value you put at each location! You won't need to specify all of the 32x8 locations.

I suggest you draw yourself a memory map. The smallest item you must map is 8Kb, so how many blocks will it have to cover 64Kb? How many address lines are involved in selecting one block? If less than the number required by the ROM, what are you going to do with the others? For each block, note the value of those address lines, and the value of the two select output bits. Now it is almost trivial to write out the content of the PROM. It will contain a lot of "don't care" bits.

Side note: only archaeologists make such systems from separate chips these days, and even micro*controllers* are switching from 8 bit to 32 bit. But the design of something like this is still a good test of your general knowledge of digital logic.