Electronic – Protecting 3.3V I2C lines

Per your comment, your GPIO pins are not open-collector but are forcing both high and low. I2C requires open-collector on both the clock and data lines. Without this, the slave cannot, for example, ACK by pulling the data line low (since the master is actively pulling it high).

If you cannot set open-collector mode, another way is to leave the output data bit low and switch the pin mode between output (low) and input (effectively open-collector).

I suggest you get a I2C compatible bi-directional buffer with tri-state/high impedance mode using "ENABLE" style signal.

I found one by NXP called the PCA9517A (which is on digikey for $1.37 a piece or 59c in bulk) which does all of the above, plus allows for voltage level shifting and defeats bus capacitance issues! The same signal used to remove power from the RPI can be used to drive the enable pin, thus detaching that whole side of the I2C bus from the AVR's side.

Another note about the PFET circuit you show - you need a logic-level gate voltage PFET, and you need to use a BJT to properly turn the PFET on/off, and at least put the pull up resistor there.

It should look more like this to operate correctly:

^{simulate this circuit – Schematic created using CircuitLab}

Please realize that the capacitors I show are very important, the RPI needs good power supply decoupling and heavy duty bulk capacitance nearby, I suggest you place the capacitors as close as you can to the RPI's 5V input.