Electronic – provide a negative input voltage to this (or any) ADC

Amplifier U1 helps to make the circuit as close to "ideal" as possible. In the pH cell the impedances involved re very high and any variations from ideality are reflected in the results.

The "challenge" is given in the following section from the application note:

• The output of amplifier U1, which is set up in a unity-gain configuration, biases the reference electrode of the pH electrode with the same voltage, 512 mV, at low impedance.

  The pH-measuring electrode will produce a voltage which rides on top of this 512 mV bias voltage. In effect, the circuit shifts the bipolar pH-electrode signal to a unipolar signal for use in a single-supply system.

ie any error in this voltage is directly reflected in the output voltage as an error in pH reading.

The source impedance of the 2 x 10 k resistors in series is 5 K ( Reffective = R1 x R2 / (R1+ R2)). If the cell were to load this with a 1 megohm impedance the change in actual voltage would be 5k // 1 M = 0.005 = 0.5%. Loading with 10 Megohm would give 0.05% error etc. This does not sound much (& isn't much) but the sensitivity of the cell is 1 mV per pH. So 5/1000 x 512 mV ~= 2.5 mV or 2.5 pH error. And 10 megohm loading = 0.25 pH error. Even 100 megohm loading = 0.025 pH error.

If pH is read to even 0.1 pH units an error of 0.025 pH is 1/4 of a "bit". If pH was read to 0.01 units then 0.025 pH = 2.5 "bits " - and that's with 100 only megohm load!

Reducing R1 & R2 to 1 k or 100 ohms would help, at the expense of increased current drain U1 provides a better solution at acceptable cost.

Also, can anyone tell me when I have a 0.02V reading all the time?

This is likely the basic error in the ADC when connected to a source of very high impedance (1Mohm in parallel with the piezo). It is likely that ADC "doesn't like" high impedance signals and also any input bias currents will create a sizable DC error as you have seen. This is what the data sheet says: -

For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2.

As for centralizing the signal, and assuming 1Mohm shunt resistor, split it into 2x 2Mohm resistors; one to ground and one to the reference voltage used by the ADC. You might also consider putting a 1 kohm resistor in series with the ADC input pin because, from what you said in your question, there could be significant voltages produced by the piezo and the 1 kohm would off some protection.