DRAM, as you said, basically consists of a storage capacitor and a transistor to access the voltage stored on that capacitor. Ideally, the charge stored on that capacitor would never decrease, but there are leakage components that allow the charge to bleed off. If enough charge bleeds off the capacitor, then the data cannot be recovered. In normal operation, this loss of data is avoided by periodically refreshing the charge in the capacitor. This is why it is called Dynamic RAM.
Decreasing the temperature does a few things:
- It increases the threshold voltages of MOSFETs and the forward voltage drop of diodes.
- It decreases the leakage component of MOSFETs and diodes
- It improves the on-state performance of the MOSFETs
Considering that the first two points directly reduce the leakage current seen by the transistors, it should be less of a surprise that the charge stored in a DRAM bit can last long enough for a careful reboot process. Once power is reapplied, the internal DRAM system will maintain the stored values.
These basic premises can be applied to many different circuits, such as microcontrollers or even discrete circuits, as long as there isn't an initialization on start-up. Many microcontrollers, for example, will reset several registers on start-up, whether the previous contents were preserved or not. Large memory arrays are not likely to be initialized, but control registers are much more likely to have a reset on start-up function.
If you increase the temperature of the die hot enough, you can create the opposite effect, of having the charge decay so rapidly that the data is erased before the refresh cycle can maintain the data. However, this should not happen over the specified temperature range. Heating the memory hot enough for the data to decay faster than the refresh cycle could also cause the circuit to slow down to the point where it couldn't maintain the specified memory timings, which would appear as a different error.
This is not related to bit-rot. Bit-rot is either the physical degradation of storage media (CD, magnetic tapes, punch cards) or an event causing the memory to become corrupted, such as an ion impact.
This is one of those situations in which you're going to want to set up your logic analyzer for synchronous sampling (external clock) rather than asynchronous sampling (internal clock). Connect the LA's external clock input to the SDRAM clock signal.
This way, each sample on the LA will contain one word of data from the SDRAM's data bus.
Yes, it's true that if you wanted to look at a clock waveform at 133 MHz, you'd need to have a sample rate of at least 266 Msps, but that's not what you're interested in here. Keep in mind that the data lines only switch high or low at the 133 MHz rate, so the fastest square wave you'll see is actually 67 MHz.
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Perhaps I can add a little simple information. As I understand it, POD (Pseudo Open Drain) drivers, have a strong pulldown strength but a weak pullup strength. A pure open-drain driver, by comparison, has no pullup strength except for leakage current; this is why the term "pseudo" is used. The remaining pullup strength is provided by parallel-terminating the receiver at the far end to the HIGH voltage, often using a switchable, on-die terminator instead of a separate resistor. The purpose of all this is to reduce the overall power demand compared to using both strong pullup and strong pulldown, as in drivers such as HSTL. DDR4 memory uses POD drivers, replacing push-pull drivers in DDR3 that drove strongly in both High and Low states.