Electronic – PWM Control using Verilog problem

controlfpgapwmverilog

My PWM control is having issue,I don't know why…

So I'll briefly describe my PWM specs;

a 4-bit Input named value,

Input clock 50MHz,

a single bit output PWM_out,

Duty cycle is equal to 1/16 of input clock and

it changes when the value input is changed.

like, Value = 0000, Duty Cycle=0%

Value = 0001,Duty Cycle=6.25%

Value = 0010,Duty Cycle=12.5%

Value = 0010,Duty Cycle=18.75%

…. etc

when value changed,duty cycle should be increased by 6.25%

Here is my code and output doesn't seem correct;

module pwm_c(clk,value,PWM_out,counter);
input clk;
input [3:0] value;
output PWM_out;
reg PWM_out;

output reg [3:0]counter;

//parameter rst=1;

always@(posedge clk)
    begin
        if(!rst)
            counter <= 4'd0;
        else
            counter <= counter + 4'd1;
    end

always@(counter or value)
    begin
        if(value == 4'd0)
            PWM_out = 1'b0;
        else if(value == 4'd1)
            PWM_out = (counter >=4'd1) ? 1'b0:1'b1;
        else if(value == 4'd2)
            PWM_out = (counter >=4'd2) ? 1'b0:1'b1;
        else if(value == 4'd3)
            PWM_out = (counter >= 4'd3) ? 1'b0:1'b1;
        else if(value == 4'd4)
            PWM_out = (counter >= 4'd4) ? 1'b0:1'b1;

        else if(value == 4'd5)
            PWM_out = (counter >= 4'd5) ? 1'b0:1'b1;
        else if(value == 4'd6)
            PWM_out = (counter >= 4'd6) ? 1'b0:1'b1;
        else if(value == 4'd7)
            PWM_out = (counter >= 4'd7) ? 1'b0:1'b1;
        else if(value == 4'd8)
            PWM_out = (counter >= 4'd8) ? 1'b0:1'b1;


        else if(value == 4'd9)
            PWM_out = (counter >= 4'd9) ? 1'b0:1'b1;
        else if(value == 4'd10)
            PWM_out = (counter >= 4'd10) ? 1'b0:1'b1;
        else if(value == 4'd11)
            PWM_out = (counter >= 4'd11) ? 1'b0:1'b1;
        else if(value == 4'd12)
            PWM_out = (counter >= 4'd12) ? 1'b0:1'b1;

        else if(value == 4'd13)
            PWM_out = (counter >= 4'd13) ? 1'b0:1'b1;
        else if(value == 4'd14)
            PWM_out = (counter >= 4'd14) ? 1'b0:1'b1;
        else if(value == 4'd15)
            PWM_out = (counter >= 4'd15) ? 1'b0:1'b1;


        else
            PWM_out = 1'b0;
    end

endmodule

Although I've asked a friend who knew a little more about Verilog than me,
He said,
I have to divide the input value by 16,per value is equal to 16 clocks of input clock.
I don't quite understand how to implement this…
I don't understand how to divide value input,'cause in my thoughts that's 4 manual switches or wires..
How do you divide something that's controlled manually?

Please anyone help me…Thanks…

edit;
adding all and each suggestions,still not the result I expect.the third picture is by far I tried to get as close as I wanted,but if you look at the value,It still doesn't divided by 16 and PWM_out starts to have output from value=3 not value=1…

edit2;
So I asked my friend once more,and it suggested that value has to 16 times of clk,which means I have to make value changes after full 16 pulses of clk,but I just haven't have the faintest idea to implement this.

maybe I wasn't cleared enough…down below is what I transit in my brain of above's suggestion..

value has to be full 16 cycles of clk before change,and then PWM_out to output…like,value=0,PWM_out=0 and value changes after 16 pulses of clk, value=1,PWM_out=1,value changes after 16 pulses of clk…so on and so on… each time it change the PWM_out is wider and wider like, value =0,PWM_out=0, changes after 16 pulses of clk,value=1,PWM_out=1(equal to almost one pulse of clk) , value=2,PWM_out=2(equal to one pulse of clk)…so on.

the PWM_out should be close to the third picture,but should be from tighter to wider and the value has to match the full 16 cycles of clk.

edit3:
Okay,so I think maybe I take the third picture's wave result to draw out what I described in edit2…maybe the drawn picture would much better to help to think…drawn picture in Fifth Picture.

Best Answer

Compiling the information you added later the following should work:

module pwm_d
(
    input   wire    rst,
    input   wire    clk,
    input   wire    [3:0] cmp_value,
    output  wire    PWM_out,
    //for debugging
    output  reg     [3:0] clk_counter
);

reg [3:0] stored_cmp_value;

assign PWM_out = clk_counter < stored_cmp_value;

always @(posedge clk or posedge rst) begin
    if(rst) begin
        clk_counter         <= 4'd0;
        stored_cmp_value    <= 4'd0;
    end else begin
        clk_counter         <= clk_counter + 4'd1;
        stored_cmp_value    <= clk_counter != 4'd15 ? stored_cmp_value : cmp_value;
    end
end

endmodule

and the testbench:

module simulation();

    reg clk_x1;
    reg rst;  
    reg [7:0] counter_A;


pwm_d UUT(
        .clk(clk_x1),         
        .rst(rst),
        .cmp_value(counter_A[7:4])
    );


initial begin                                         
    rst = 0;  
    clk_x1 = 0;
    counter_A = 0;
    #50 rst = 1;
    #200 rst = 0;
end

always begin
    #1 clk_x1 = ~clk_x1;
    counter_A = counter_A + clk_x1;
end

endmodule

This way the comparsion value will only change for every new cycle. Basically the only real issue with the already tried/suggested solutions is that the compare value is changing "to fast"/ at the wrong time.

EDIT: corrected source. The module does not work for a 100% PWM (so always on) case. EDIT2: added testbench.

Related Solutions

Electronic – Random bit sequence using Verilog

You probably do want something like the circuit shown by clabacchio.

This is easily rendered in Verilog as

reg [4:0] d;
always @(posedge clk) begin
    d <= { d[3:0], d[4] ^ d[2] };
end

This is, as others mentioned, a linear feedback shift register, or LFSR, and it generates the maximal length pseudo-random bit sequence that can be produced with a 5-bit state machine. The state machine traverses 31 states (\$2^n-1\$, where n is the number of registers) before repeating itself.

Of all the states that can be encoded by 5 registers, only one is not used, which is the all-0's state. The all-0's state is a lock-up state --- if the state machine gets into that state by an error, it will be stuck permanently in the all-0's state, as you can see because 0 ^ 0 = 0. This means you have to be sure (using a synthesis directive in the Verilog or constraints file) that the registers don't initialize to the all-0's state.

If you need the all-0's state not to lock up, you can use an XNOR in place of the XOR gate, and get a sequence that includes the all-0's state and locks up in the all-1's state.

Also be aware that the longest run of 1's produced by this state machine is 5 in a row, and the longest run of 0's is 4 in a row. This can be important if you are using the PRBS to test a system with ac-coupling...longer runs will stress the system more.

In communications testing, longer sequences are more common, mainly to exercise more of the low frequency behavior of the system:

PRBS7

reg [6:0] d;
always @(posedge clk) begin
    d <= { d[5:0], d[6] ^ d[5] };
end

PRBS23

reg [22:0] d;
always @(posedge clk) begin
    d <= { d[22:0], d[22] ^ d[17] };
end

PRBS31

reg [30:0] d;
always @(posedge clk) begin
    d <= { d[30:0], d[30] ^ d[27] };
end

Notice that it is not always the final two registers that are "tapped" to generate the incoming bit of the shift register.

Xilinx app note XAPP052 gives a handy table of connections to be used to generate any size PRBS from 3 to 168 registers.

App note XAPP211 shows how to implement them efficiently in Xilinx devices. Essentially, a single look-up table in a single logic block can be used to implement up to 32 registers worth of shift register (depending on architecture).

LFSRs can also be used to implement a counter efficiently if you don't care about the intervening states, just how long takes to count down to some terminal value.

Problem compiling verilog

One possible cause: Synthesis is merging vga_g, vga_b, and vga_r into a single net, because they are all equivalent. Then the translate step can't put them in different locations, because there's only one net in the synthesis output.

Solution 1. Explicitly instantiate your OBUFs.

 OBUF obuf_vga_g ( .I ( on ), .O ( vga_g ) ); 
 OBUF obuf_vga_b ( .I ( on ), .O ( vga_b ) ); 
 OBUF obuf_vga_r ( .I ( on ), .O ( vga_r ) );

This makes it explicit in your code that the output nets are buffered from the on signal and attached to output pins. Obviously the tool should already know these nets are connected to output pins because they're outputs of the top level module. Having to do this kind of thing is just one of the quirks of using a tool originally designed to describe logic for the different purpose of designing logic.

Solution 2. Use constraints to eliminate merging of duplicate logic.

Depending on which synthesis tool you use, there should be a constraint available that you can attach to your vga_b, etc, signals to prevent them being merged in the synthesis step. In Synplicity, I believe you would use syn_keep to prevent removing redundant combinatorial logic.

As Apalopohapa noted in a comment, you might also need to turn on a flag to enable Synthesis to automatically generate the OBUFs you need. This should default to 'on', but it doesn't hurt to double-check it.

Best Answer

Related Solutions

Electronic – Random bit sequence using Verilog

Problem compiling verilog

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