# Electronic – Question about the Inrush Current in LDO

capacitorinrush-currentldo

I have a doubt with inrush current limiting for an LDO. To understand that, I referred old literature of capacitors and others. I have some conflicting arguments which I need to clear out:

1. This is from Wikipedia:

The current into a capacitor is known to be
: the peak inrush current will depend upon the capacitance C and the
rate of change of the voltage (dV/dT). The inrush current will
increase as the capacitance value increases, and the inrush current
will increase as the voltage of the power source increases. This
second parameter is of primary concern in high voltage power
distribution systems. By their nature, high voltage power sources
will deliver high voltage into the distribution system. Capacitive
loads will then be subject to high inrush currents upon power-up.
The stress to the components must be understood and minimized.

This passage says that inrush current depends upon capacitance
value, voltage to applied to it.

2. From my basic understanding: for sudden changes the capacitor is a short and the capacitor will not allow any changes in voltage suddenly. So, when we turn ON power at that instant C will be short having 0 voltage across it. So the max current will depends on the ESR of cap and any series path resistance. It doesn't depends on the capacitance value.
This passage says: Inrush current depends on ESR of the cap and not on value of capacitor, which contradicts the previous passage.

From all these how can we calculate how much transient will there be?

One more confusion: most of the regulators specify controlled slew rate of the output to mitigate this inrush current limiting problems. But the slew rate limiting will work for capacitors connected on the output side. But there will be capacitors that will be connected on input side of the regulator. Will those have large currents?

You are assuming the capacitor will be a true short, which it won't be, the voltage will never rise infinitely fast - remember there is inductance and resistance in real life to limit things. If we look at the formula for current through a capacitor:

\$I = C \cdot \dfrac{dV}{dt}\$

We can see that I depends on the cap value and how fast the voltage source rises. The formula does not include the ESR though, so we have to allow for this separately.
This means that both the cap value/rise time and/or the ESR can limit the peak current - roughly meaning if the rise time is fast enough, the peak current will be limited by the ESR. If the result of the formula above is much lower than V/ESR though, then it will be limited by the capacitance value, or voltage rise time.
You can see both effects at once - initially at turn on with a fast rise time, there will be voltage divider effect between the wiring resistance and the ESR, then the capacitor charges as it would normally.

If we look at a couple of examples, using the same risetime of 1ns to 1V, but different ESR/Cap Value/Wiring Resistance.

With a 100uF Capacitor, 1mΩ ESR, 1mΩ Rwiring:

With no ESR, we would expect I = 100uF * (1V/1ns) = 100kA. However, the resistance of the wiring and ESR of the capacitor divide to limit things to 500A initially, then the capacitor charges to 1V.

Now if we reduce the capacitor value to 10pF, but keep everything else the same, the current is limited by the capacitance value: I = 10pF * (1V/1ns) = 10mA:

The ESR has no effect here.

Now if we simulate a more realistic situation with the 100uF capacitor, wiring inductance of 100nH and increased resistance of 10mΩ wiring resistance and 50mΩ ESR we get something like this, where everything works together to limit peak current:

These are very simplistic simulations, you could go on and add the capacitors ESL, leakage current, wiring parasitic capacitance, etc.

About the capacitors on the input side of the regulator, without limiting they will be subject to large currents at power up regardless of the slew rate limiting on the output side.