I'm new at the circuit design biz. I'm designing a battery powered device around the TI TPS61025 boost converter, and I'm rather confused about the proper range for the low-ESR output capacitor. The data sheet says says
With the calculated minimum value of 24 μF and load transient considerations the recommended output capacitance value is in a 47 to 100 μF range. For economical reasons, this is usually a tantalum capacitor. Therefore, the control loop has been optimized for using output capacitors with an ESR of above 30 mΩ.
So I understand I want a cap in the 47-100 μF range with an ESR of at least 30 mΩ. But what's a reasonable upper limit for the ESR? Is there an upper limit?
Best Answer
This is hard to answer without knowing the what exactly is going on inside the control loop, which is probably not described with much detail in the datasheet. Saying it is "optimized" for 30 mΩ doesn't say what it really needs or what happens when it's not exactly 30 mΩ. Since they make a issue of the output cap ESR, there should be a min/max ESR spec elsewhere in the datasheet.
Hopefully 0 ESR is OK, else it gets inconvenient. Lower ESR is generally better, and certainly closer to ideal, for a capacitor. Capacitor spec sheets therefore often only spec maximum ESR. In that case you either have to get the guaranteed minimum from the capacitor manufacturer, or add deliberate resistance. A better answer is to stay away from chips that specify a minimum output cap ESR to be stable.
That chip is probably old, as ceramic capacitors have come a long way in the last few years. These have much lower ESR than tantalum, and can now approach such capacitances at reasonable cost. Newer chips now make use of the lower available ESR to get better performance instead of requiring the capacitor to have a high resistance. This is a all around better strategy.