In my current project I need a high-side PMOS to disconnect a load once a over-current or (downstream) over-voltage condition is detected. Obviously without a permanent latch, once the PMOS opens, an over-current as well as over-voltage will disappear, which would let the comparators re-close the PMOS. This is all fine since I generally assume transient faults, that should disappear after power-cycling. However, should a permanent fault occur, the PMOS would alternate between open and closed state rapidly, which in case of a short would lead to high high pulsed current that drain the batteries quickly.
Therefore I need a minimum-off timer to keep the PMOS in open state for a short (20ms – 50ms) duration after a fault has been detected. This would allow return into operational state for transient faults, while also minimizing the impact of permanent faults.
I know that there are ready-made IC like the LTC4364 and similar from MAXIM but these seem to be in short supply at least in small quantities and are also rather expensive.
My current approach, without the minimum-off timer, looks like this:
simulate this circuit – Schematic created using CircuitLab
My first bet was the venerable 555 timer or other general purpose retriggerable monoflop but my supply voltage requirement of Vin,max 36V rules out all parts that I am aware of. Please correct me if I am wrong!
This leaves me with a discrete solution, resorting to a BJT monoflop. It is triggered by the OK open-collector output of the comparator. When a error occurs, OK is pulled low and C1 discharges, all while the PMOS gate is pulled up by the PNP of the first schematic. When the PMOS opens, the comparator also stops pulling OK low but slowly charging C1 keeps it there for some time.
Please review by schematics! I am especially unsure about the working of the monoflop, since I have the feeling I might be using it in a slightly unusual way. I also have not yet breadboarded the thing but only simulated in LTSpice so far (which works fine).
Clarification: Vin, max 36V is only the maximum fault withstand voltage. Maximum working voltage is 12V.
Best Answer
I'll cut to the chase and suggest a modification to your main diagram: -
Use a diode as shown so that activating Q1 is done fairly quickly when an "overload" occurs. To make this work effectively Q1 should be a P channel FET - this will allow C1 to charge to nearly the incoming power rail - in fact add a zener diode across R2 to limit this charge to 10V (in case the gate gets damaged by over-voltage).
R2 can be chosen to be a high value that slowly discharges C1 when "OK" returns high.