Electronic – Relaxation oscillator

Simulated oscillators usually don't start on their own, try setting an initial condition to break the feedback loop during the bias point calculation. I can do this with the Pulsonix (SIMetrix) SPICE simulator by adding an initial condition with a value of zero, you should be able to do something similar with the simulator you are using - see the documentation.

If you don't want to use passive components, here is an all digital solution. I realize using the counter chips goes beyond your desire to use only basic logic gates (NAND, NOR etc.), and indeed one can construct the counters used below from these elements, but the complexity would make it impractical.

Take your first oscillator, and add two more inverters. The typical propagation delay t_tpd of a 74HCT04 inverter is 14 ns. This will result in an output frequency of approximately 70 MHz (which I simulated in CircuitLab). The reason for using the lower frequency is two-fold; it allows a greater choice in parts for dividing down (for example the 74HC4024 part below has a maximum frequency of 90 MHz), and 70 MHz divides down closer to 1 Hz than 120 MHz using binary counters.

Using a 74HC4024 7-stage ripple counter, use the Q4 tap to divide the 70 MHz by 32, giving a frequency of approximately 2.19 MHz.

Then using a CD4521 24-stage counter, use the Q18 tap to divide 2.19 MHz by 262144 giving a frequency of 8.34 Hz. Using the tap Q21, dividing 2.19 MHz by 2097152 generates 1.04 Hz. Using the last tap Q24, dividing 2.19 MHz by 16777216 give 0.13 Hz.

So, not quite the full range you asked for (0.1 to 10 Hz), but close (0.13 to 8.34 Hz, including 1 Hz almost exactly), and there are an additional four taps in between that can be used.

This would take three IC's -- the five inverters in one 74HCT04, and the two counters.