Electronic – Role of capacitor in this circuit

The data terminals in USB are high speed differential lines, you don't want to put any capacitance on those lines (it would kill your signal basically). You want to use some ESD protection devices on the data terminals though, to protect the data pins from getting destroyed by static discharge.

The 10nF capacitor on the 5V line together with the ferrite bead will filter out some noise picked up from the cable but also coming from the FTDI chip. So it will improve the EMI performance and will not disturb your USB host.

I don't think the bottom part is optional but mandatory as well. The 4.7µF capacitor will store some energy which will acts as a pool the FT232R can take from without the parasitic inductance and resistance of the wire affecting it much. The 100nF capacitor is just your standard value decoupling capacitor to improve the noise performance of the FT232R.

The 10nF capacitor is not a break in the DC circuit. As you can see the GND node is also on the GND pins on the FT232R, so the current will gro from VCC through the FT232 to the GND node and back to the host.

Roughly speaking, your schematics can be reduced as follows. The top schematic is as you laid them out (with just a little less "dross" to confuse things.) The schematic below each is the equivalent, reduced version using a Thevenin equivalent for your resistor divider.

^{simulate this circuit – Schematic created using CircuitLab}

It's a little more obvious, now.

Circuit 1, of course, exhibits \$6\:\textrm{V}\$ when the output is unloaded. The Thevenin source voltage simply appears at the output, since there is no current in the Thevenin resistor.

Circuit 2 will track \$V_4\$, also for obvious reasons. \$V_4\$ is directly driving the output. The \$6\:\textrm{V}\$ Thevenin source voltage is behind a \$5\:\textrm{k}\Omega\$ resistor and can't interfere.

Circuit 3 isn't really much more complex. Capacitor \$C_1\$ charges up to the Thevenin voltage of \$6\:\textrm{V}\$ (given time) and after that the voltage of \$V_8\$ is simply jacked up by \$C_1\$'s voltage. So if \$V_8\$ is \$0\pm 1\:\textrm{V}\$, then after \$C_1\$ the voltage is \$6\pm 1\:\textrm{V}\$.

The only question really is how it is that \$C_1\$ gets that voltage. It does, because \$V_8\$ averages \$0\:\textrm{V}\$ over time and since there is a \$6\:\textrm{V}\$ Thevenin voltage behind \$R_{TH}\$, \$C_1\$ will charge up to the average of the difference. Once it does that, as \$V_8\$ rises up a little, then there will be some current flowing from \$C_1\$ back to the Thevenin voltage, and as \$V_8\$ falls below a little, then there will be some current flowing from the Thevenin voltage back to \$C_1\$. But once \$C_1\$ reaches a mean value of \$6\:\textrm{V}\$, the amount of charge leaving \$C_1\$ in one half of the cycle will exactly equal the amount of charge returning to \$C_1\$ in the other half of the cycle. And then everything is in equilibrium.

Another way of viewing Circuit 3 is that \$R_{11}\$ and \$R_{12}\$ form a voltage divider with \$6\:\textrm{V}\$ in the center and that \$C_1\$ will develop a voltage across it equal to the average difference. It charges up for a bit, while that happens, and so for a short time (several times the \$C_1\cdot R_{TH}\$ time constant) there will be an imbalance. But that imbalance will be just what's needed to charge up the capacitor until it reaches that equilibrium point where the charge leaving equals the charge arriving and the mean value then no longer changes.