Absolutely, absolutely ABSOLUTELY the power symbols.
Anyone who uses net labels (local or global) for power distribution should be fired.
The entire purpose of power symbols is to allow them to be quickly visually distinguished from local or global net labels, allowing the schematic to be more easily read and maintained.
I have dome a fairly significant amount of work troubleshooting and cleaning up schematics drawn completely with net labels, and it's a nightmare.
Furthermore, if you have to use net labels for some weird reason, strictly follow the local-global hierarchy. Many EDA packages let you set all net labels as global. If you do this, please die in a fire.
Only use global net labels when you have to. Nets should be local by default.
An even better option is to use an EDA package that enforces hierarchical schematic interconnects. This way, each schematic is represented as a "meta-component" on a higher-level schematic. Basically, every global net-label on each schematic is reflected as a pin on an higher-level drawing.
This makes the sheet-to-sheet interconnections immediately clear, and lets you trace out where, exactly, a net label routes.
Also, you should only ever have one global net label of every name on a sheet. If you have two devices that need to connect to that global net wire them together with a schematic wire. This is vital in situations where you are not the only person working on a schematic, and useful in all others, because it makes the schematic much more intuitively understandable.
Frankly, net labels are very, very overused as it is. The only situation where you should chose a net-label over actual schematic wires is when it improves readability. Unsuprisingly, this happens very rarely.
I see a lot of schematics these days that are basically a random assortment of chips tied together with net labels.
This is a ABSOLUTELY HORRIBLE way to do schematics.
If you have ever spent time tring to understand or modify a schematic drawn by someone else, which is based around net labels (particularly if it's complex), you will hate them with the fiery passion of a thousand suns.
NET LABELS ARE ANTI-MAINTAINABILITY.
They are (rather literally) the GOTO statements of schematics.
They connect somewhere else, and you have to manually find it (unless your EDA package lets you follow nets, but then, what if you're working on paper documents?). They may completely break out of the local document structure. They may have non-obvious effects, and mis-spelling things can cause errors which the DRC checking will not catch, because enforcing rules on net labels can be difficult.
One thing of note is that, (as Brian Carlton points out in a comment), that using net-labels to indicate the function of an existing wire is a very good thing to do.
Net labels are only GOTO-like if they are connected by name. Otherwise they can just help debugging. For example DATA0 between a uC and SRAM on the same page.
What's considered the maximum number of parts on a single page?
Depends on the size of the page. You can fit more on a D-sized plotter sheet than a B-sized (roughly A4) sheet. Don't crowd things to the point it gets difficult to read.
What to consider when making a schematic multiple pages?
Almost all my designs end up as multiple sheets. Sometimes the manufacturing guys cut them all up and paste them together in one big plotter sheet to make it easier to follow the signal flow. But normally I don't print out bigger than 11x17 so I work at that size.
Something you didn't ask: I tend to make the first sheet be the critical input and output connections of my circuit, and work up towards more complex circuits on later pages. Other people like to put the critical signal path parts on the first page, and the input and output connections end up deep in the stack of schematics. I'm not sure which is really better.
When should I consider putting multiple tracks into a buss?
I rarely do this, but its a matter of style (and convention in your workgroup).
How should I name busses, netlists, and the references to other pages?
I tend toward all-caps net names, but otherwise I don't have fixed rules. More disciplined organizations might have more detailed rules.
How should I place components to minimize the number of nets?
I prefer to place components to make the signal flow clear. I don't worry about the number of named nets.
What kind of comments should I include on a schematic?
Anything important for the layout guy to know (matched length traces, place bypass caps near ICs, etc.) Anything a future engineer might need to know if they're looking to replace an obsolete part. Non-obvious critical specs like higher-than-normal resistor power requirements or tight tolerances. Anything that has to be tuned in production (Like "tune pot to achieve 50% duty cycle" or whatever).
Where should I place the designation and value for horizontal and vertical components? Does it matter as long as I stay consistent?
I use vertical text for vertical components to allow more parts to fit cleanly on a sheet. Others (apparently) consider this a grave sin. Be consistent and be consistent with others in your organization.
Should I note component packaging & rating on the schematic? Meaning discrete vs SMD or if a specific resistor is high powered?
Specifying the package type for each part visibly on the schematic would be clutter. But obviously that information has to be in the design to get transferred to layout. As mentioned above mention nonobvious specs that might trip someone up if they have to replace an obsolete part or find an alternate vendor due to a shortage.
Your BOM (Bill of Materials) will need to specify an exact manufacturers part number (or a list of acceptable alternates called an AVL "approved vendor list") for each part.
Should I customize nets in different colors or widths?
I don't recommend this. I'd prefer to get schematics that make sense if printed out in black & white.
How should I version control schematics?
I store datecoded backups (like "mydesign_20120205.zip" on my own pc and a remote share drive. Definitely store a backup whenever you release a design (either to layout or to manufacturing).
Edit: There are better ways to do this (see comments) but a simple process like dated zip files is also perfectly workable.
What workflow should a single person use to keep designs organized?
Keep backups. Use all the tools you have available. If you aren't doing your own layout, keep good communication with the layout guy.
Best Answer
Naming of things is an important topic. Software people perhaps discuss them more than most, as they have lots of variables and functions to name. Fortunately, you have only a handful.
Names have to meet a number of requirements.
Be meaningful - you shouldn't have to look it up in a cross reference to understand it.
Not cause confusion - not only be unique in scope but also not share too many leading characters with other names
Be easy to use - a 50 character descriptive name takes a long time to read, and is easily mis-typed
Not look weird? I don't think so. Who are you doing this schematic for? It's not to look pretty, it's to be correct. If you have an unusual requirement of several rails, all of about 3v, that you must not get mixed up, then weird looking names might be an asset rather than a liability.
There are conventions, like VCC and 3v3, which are not applicable to your situation. So you need to identify the function of these two rails, in a way that's meaningful to you, won't confuse you, and will tolerate small changes to the voltage later. Are they '3v_and_a_bit' and 'nearly_3v', or '3v_logic' and '3v_memory', or '3v_DSP' and '3v_analogue'. I'd often have rails like '3v3_raw', 3v3_filt1' and '3v3_filt2' when using supply filters to stop parts interfering with each other via the rails.