Electronic – Selecting proper vales of Rb, Re and and Rbe in a NPN transistor emitter follower configuration

digital-logicswitchestransistorsuart

I need to gate a TTL Tx pin @115000bps as the chipset that drives the RxTx lines do not implement UART BREAK for arbitrary time periods.

As a quick hack I have come up with the following configuration that I will connect to the TTL Tx pin of the said chipset, at TTL.TX.In.

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The Tx output from the whole device will be tapped from TTL.TX.Out

BREAK is the gating input that controls whether TTL.TX.Out will be in BREAK condition or not.

The TTL levels can be ~5V DC or ~3v3 DC.

My questions are:

  1. What should be the proper value of Rb, Rbe and Re?
  2. Is this a proper design that will allow me to implement BREAK for arbitrary time periods without affecting the "usual" transmission?

My fears are:

  • i. The Vce drop, typically 0.7V can degrade the output signal quality (although I measured 0.05V Vce drop – are these old transistors that efficient now?)

  • ii. By driving the transistor too hard and @115000bps, the UART signal outputs could become severly degraded

Of course, in this case the transistor really should not affect TTL.TX.Out as it acts like a simple switch that either grounds TTL.TX.In or not, but I would like to ally any concerns that this design can cause problems down the line.

Best Answer

No, your solution will affect normal transmission. When the collector of the transistor is driven low (while the "break" signal is high), the "break" signal will drive current through the two 1K resistors and the B-E junction of the transistor, holding the output (the emitter) at almost Vcc/2.

What you really want is an ordinary AND gate. When both inputs are high, the output is high, but if either input goes low, then the output goes low. Note that you can purchase single gates in SOT23 packages for applications like this. Look for the NC7SZ family from Fairchild, or the MC74VHC1GT family from OnSemi. This would be the preferred solution.

Since you asked, you can make an AND gate out of diodes, too (just reverse them from the OR configuration and use a pullup instead of a pulldown as a load). You could even use one of your NPN transistors as a dual diode. Also, you could use a second NPN transistor as an emitter-follower buffer, which would cancel out the level shift caused by the diodes. See below:

Circuitlab schematic

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