Electronic – Sensitivity list rule in HDL

hdlverilog

I have a little confusion about sensitivity list rule: all signals that are read in the always block must be included in the list. When including the posedge CLK and EN in my sensitivity list, I get value of x changed when either of signals in the sensitivity list changes. Thus, if EN changes in the middle of the clock cycle, x changes accordingly, which is expected. However, this is not the outcome I wish to get:

always @(posedge CLK, EN)
if(EN)
    x <= 1;
else
    x <= 0;

I need the value of x to change only at the rising edge. Therefore, I remove the EN from the list to achieve desired outcome. But then, this violates the rule.

This is, probably, a very trivial question, but could someone clarify what's the proper way to implement it?

Best Answer

Forget that rule. Here's a simpler one:

  • If you want sequential logic, use always @(posedge clock) (or negedge). You don't need to mention any other signals in the sensitivity block.

    (You can sometimes also use sensitivity lists like always @(posedge clock or posedge reset) for reset signals, but don't try to get too fancy. It's very easy to create something that won't synthesize.)

  • If you want combinational logic, use always @(*).

    This is a shorthand (introduced by Verilog-2001) that makes the block sensitive to every signal that's used in it. There's no reason to name every signal anymore -- that syntax is obsolete and unnecessary.

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