Electronic – Simple low pass digital filter implementation for non-uniform sampling

A delta-sigma modulator, used in both ADCs and DACs, comprises a difference (delta) circuit that measures the error between the input signal and the feedback signal, followed by an integrator (sigma), a quantizer (often just a comparator that yields one bit of information) and a time-domain sampler. The output of the sampler is fed back to the difference circuit through a suitable inverse quantizer (i.e., 1-bit DAC).

The trick to understanding noise shaping is to consider the quantizer as linear summing circuit that adds a "quantization noise" signal to the output of the integrator. You can then use superposition to separately evaluate the effect of the circuit on both the original signal and the quantization noise "signal".

For the original signal, the integrator is in the feed-forward path, and as you might expect, it acts as a low-pass filter for that signal — high frequencies have lower gain than low frequencies.

However, for the quantization noise signal, the integrator is in the feedback path, which means that overall, the circuit functions as a high-pass filter for the noise, reducing its gain in the low frequencies (where the desired signal is) and increasing it at the higher frequencies, where it will be subsequently removed by another filter.

It is this noise shaping that accounts for the reduction in noise density in the final passband.

There is great flexibility in the design of a digital filter. You can design digital filters that behave very similarly to analogue filters (as Andy aka described). You can also build digital filters than can be hard to reproduce in analogue such as a Linear phase filter or a Half-Band filter. Or non-linear digital filters such as Median filters that have no analogue equivalence in LTI systems.

For your requirements of "a sharp, low pass filter" I'd suggest a simple IIR of the form:

out = (1-a)in + aout

the closer 'a' is to 1 the lower the cutoff frequency of your filter.

You may well have a problem with the 1MHz sample rate and 5Hz cutoff because: a = exp(-2*pi*f/fs) where f is the cutoff frequency and fs is the sample frequency. So for your example:

a= exp(-2*pi*5/1E6) = 0.99997

If you really do need a 1MHz sample rate (because your data must be sampled by a 1MSPS ADC for example), then a 3 stage multi-rate filter is more appropriate. For this you would:

1. Average 32 values at 1MHz and output one sample out of 32 at 1MHz/32
2. Average 32 values at 1MHz/32 and output one sample out of 32 at 1MHz/32^2 (1MHz/1024)
3. Implement an LPF as above with a 1MHz/1024 sample rate.

UPDATE BASED ON NEW INFO FROM OP: Based on your information that:

1. You are interested only in DC
2. You are not sure about the cutoff frequency because you mention 60Hz and 6kHz bandwidth but also "A cutoff frequency of 5Hz"
3. You need flexibility in sample rate

I think your best choice is a CIC Decimator.

Basically, its an MA (FIR) digital filter, made up of

1. an integrator at the input clocked at the ADC sample rate (36kHz shown),

2. a differentiator at the output clocked at the output rate.

   You can control how much filtering you get by changing the output rate.

For example with an input rate of 36kHz and an output rate of 5Hz this gives you a 36000/5 = 7200 point moving average. In reality you'd like to keep the rates as binary ratios so M=13 gives 36kHz in 36kHz/2^13 out and MA length is 2^M = 8192

The group delay of this will be 2^(M-1)/Fin or 113ms for the above example. That's one of the disadvantages of such a simple circuit but would not be a problem in a system whose DC value varies slowly.