I am studying the PowerPC architecture on the MPC5644B. The documents from Freescale mention it to be a single Issue architecture.
The data sheet states the following,
• e200z0h single issue, 32-bit core Power
Architecture compliant CPU
— Up to 80 MHz
— Variable length encoding (VLE)
— Supports Nexus3+
I did some Google search and read forums, this seems to be some kind of Mixed Harvard architecture, but i am not sure exactly what it is.
If anyone could help , it would be highly apprecieated.
Best Answer
A single issue processor is basically one instruction, one clock cycle.
Every clock cycle one thing happens. In a pipelined processor basically that means the pipeline gets shifted down a notch and a new instruction is read from memory. That of course is at its most efficient. Some instructions may take longer that one clock cycle to execute, so the pipeline would stall. But assuming all the instructions take just one clock cycle to execute, then for every clock tick you read just one instruction from memory.
That, at its most efficient, is called having "A CPI of 1", or "One Clock per Instruction".
That basically covers the majority of normal CPUs.
Now imagine a CPU which can execute two instructions for each clock tick - say one on the rising edge and one on the falling edge of the clock. So for each tick of the clock you're running 2 instructions, fetching 2 instructions from memory, etc. This is called dual issue since it's issuing two instructions per clock tick.
In this situation it's possible to get a CPI of 0.5, or half a clock tick per instruction.