Electronic – SN74HC138 demultiplexer. How to implement a switch

First, presumably you've already looked at assigning channels by geometric convenience rather than number and decided that doesn't solve your problem.

A CPLD could give you a lot of pinout flexiblity, but perhaps would be "cheating" by your goals (though there were board-level mainframe CPUs that used early PALs).

On the novel front, if your delay budget is generous an (E)PROM loaded with a suitable truth table to use address lines as channel and select inputs could be a solution. Perhaps you are already using something similar to hold a table for instruction decode or even microcode.

A more off-the-shelf solution might be to use tri-state buffers on each side, with only one enabled at a time, or even at an extreme, open-collector logic gates and a pullup.

Vee should be connected to Ground, or to a negative supply.

As this is a CMOS part, all digital inputs MUST be connected (possibly via a resistor) to either Vcc or Ground at all times - otherwise the inputs may float to a "maybe" state, with unknown consequences.

Connect all S0 - S2 and /E to ground with 10K (or so) resistors. Also connect A0 to ground with a 10K resistor, and A1 to Vcc.

Now, the output should initially be Low. Pulling S0 up to Vcc will select A1, and the output should be High.