The second technique you mention is the way to do it, using what is called a "Software Defined Radio" or SDR. Many radio amateurs are using SDRs, and the simple ones are very cheap, about 30 dollars for a kit that down-converts the input into in-phase and quadrature baseband audio output which is fed into the stereo inputs of a PC sound card for digital signal processing. However, they are using relatively low-frequency signals on the HF amateur radio bands, and the hardware doesn't use any exotic components. Digitising VHF signals as you require and receiving several channels simultaneously is going to be rather expensive, the ADC alone is going to cost about 50 dollars and you will also need an FPGA and a DSP, unless you convert down to baseband and do the DSP on a PC. You will need a lot of high-frequency design experience, be able to develop code for the FPGA, write DSP code and be able to design a high-speed multilayer PCB, so you should start studying. :)
As for cost, I'd estimate 500 dollars for the hardware, including the PCB, assuming you designed it yourself.
Linear Technology makes suitable ADCs that can downsample at 750 MHz! They were good enough to give me a couple as free samples. I have suitable FPGA and DSP boards, so it's just a question of putting them together. :)
First thing you need to recognize is that designing with a 16-bit ADC is not trivial. Even at 1 sample/s, you need to pay extreme attention to every aspect of the design to achieve 16-bit precision, or even more difficultly, 16-bit accuracy. At 130 MSa/s, everything is even more difficult.
The parts you need to do this kind of design simply won't be inexpensive. First, because of the extreme precision and careful testing needed to achieve the required performance. Second, because this kind of thing isn't done in mass-market products, so the parts aren't built in the kind of extremely high volumes that can bring the price down for everyone.
As Dave says in another answer, be sure you really need 16 bits before you go down this road. But maybe you really need 12-bit precision, and you know that if you use even a 14-bit ADC you're going to have a hard time achieving that, so you're designing with 16-bit ADC and optimize everything else as much as you can.
Another key is likely to be understanding exactly what specs you need to make your system work, and don't over-specify your clock jitter. In an SDR application, you're going to be doing math on the samples to extract specific frequency bands, etc, which will have an averaging effect over many cycles. So you might not care too much that absolutely every sample is timed perfectly, only that over your calculation interval, there isn't too much deviation from ideal timing. How much is too much, of course, depends on what kind of math you're doing and how small a signal you need to extract from how much noise.
CTS Valpey, for example, has XO's with rms jitter specs as low as 200 fs. But this spec is defined when the phase noise is integrated over a specific frequency band, 12 kHz to 20 MHz (relative to the carrier). If the total cycle-to-cycle jitter is considered, the spec jumps to 3-6 ps, depending on the center frequency.
Let me also address one comment you made in your question:
OCXO are extremely stable over time ( years ) and are usually used for that.
The "ovenized" part of that product mainly reduces the drift due to temperature change in the surrounding environment, which can be significant over time scales of minutes or seconds, not just years. It will also reduce wear on the part due to thermal cycling and improve the stability on a time scale of years.
For the < 100 fs jitter range you're looking for, you might actually need an OCXO to prevent small temperature changes affecting the performance during the time it takes to measure the jitter accurately enough to know you've achieved your spec.
My interest to eliminate FPGAs (at some other cost) is because FPGA soldering, design is a difficult process that is not properly explained by most vendors. If there is a way I could eliminate them from my design it will be great. My interest is to design something similar to this.
Best Answer
Note: we're going to oversimplify SDR hardware for illustration in this answer
ADC --> PC is (one of) the functions of the FPGA
The FPGA serves different functions in different SDR designs, but one of its primary purposes is to "just connect the ADC to the PC". I think you don't fully appreciate the process of moving data through the Universal Serial Bus (USB) and the process of capturing the radio signal.
SDR's typically require at least two ADC streams (quadrature capture after down conversion) and usually have multiple quadrature channels to do advanced things like MIMO, RADAR/Beam-forming, etc...
The FPGA is required to multiplex the digital data streams coming off the various ADC's, to format the data in a manner compatible with USB (and ultimately gnuRadio), and to receive control information from the PC/gnuRadio and effect the various changes to the ADC's and down-conversion components.
Without the FPGA you would have to implement these functions with other hardware and your design would end up much more complex, rather than the simplicity you seek. SDR designs have evolved to their current state and they are much lower cost/simpler today than they have been in years past.
Examples
Some common SDR products from Ettus and Pervices Devices illustrate the central glue-logic nature of the FPGA in these architectures. Note the placement of the FPGA between the high-speed analog converters and the relevant external data interfaces.