Electronic – Some pointers on how to begin VHDL writing

Integers are fine in synthesis, I use them all the time.

I use std_logic at top level ports, but internally I was using ranged integers all over the place

That's fine!

Be aware:

• You are simulating first aren't you :) - Integer types don't automatically "roll-over" in simulation - it's an error to go out of the range you've specified for them. If you want roll-over behaviour, you have to code it explicitly.
• They are only specced to go from \$-(2^{31}-1)\$ to \$+2^{31}-1\$ (i.e. not quite the full range of a 32-bit integer, you can't use \$-2^{31}\$ and remain portable), which is a bit of a pain at times. If you need to use "big" numbers, you'll have to use unsigned and signed.
• If you don't constrain them, you can sometimes end up with 32-bit counters where less would do (if the synth and subsequent tools can't "see" that they could optimise bits away).

On the upside:

• They are much faster to simulate than unsigned/signed vectors
• They don't automatically roll-over in simulation (yes, it's in both lists :). This is handy - for example you get early warning that your counter is too small.

When you do use vector types, you are using ieee.numeric_std, not ieee.std_logic_arith aren't you?

I use integers where I can, but if I explicitly want "roll-over n-bit counters", I tend to use unsigned.

I'm pretty sure you accidentally clicked "Verilog Module" instead of "VHDL Module":

The code generated should look something like this:

   COMPONENT mymodule
   PORT(
      clk    : IN std_logic_vector(3 downto 0);
      enable : IN std_logic_vector(3 downto 0);   
      output : OUT std_logic_vector(3 downto 0)
   );
   END COMPONENT;

Delete the accidental Verilog Module and try again paying close attention to which Source Type you choose.