Electronic – Some segments not working on 7 segment multi led digital clock

Of course it's possible. There are many companies that provide these services. The real question is whether or not you could do this at home.

You might get away without needing a SEM (Scanning Electron Microscope), that design might be done in ~3u geometry which would imagable using visible light.

You'll need a wet bench to etch off layers, like HF for SiO2 but you will also have to remove Si3N4, SiON and Aluminum. It's possible you may need a dry etch (Ar plasma in a vacuum chamber) to remove tungsten plugs in vias.

Your main issues will be measuring the exact values of resistors and capacitors (if there are any). Delineating the boundaries of substrate implants (decoration with more nasty chemicals in a wet bench) and determination of doping profiles. The doping profiles are easily obtained in a SIMS unit (Secondary Ion Mass spectrometer) but some of the structural details of implants in the FEOL (Front End of Line) can be subtle.

There will be subtle layer thicknesses that will need to measured before they are damaged or reduced in thickness by the wet etches.

There will be significant topography of the surface of the die (CMP didn't exist then) so depth of focus might complicate picture taking.

It would be unlikely that you'd be able to get the exact transistor characteristics that the original chip had easily. You'd really need to understand not just processing but transistor physics and the role of different implants.

On the positive side, if you had multiple chips (which you would need) you might be able to liberate access to a transistor and be able to put it on a curve tracer to measure directly. The feature size is large enough and being an analog chip it would probably have some large transistors in it. But there is no certainty in that.

The other good news is that you can buy old SEM's for low cost. Only a few $10K and even though they are grainy this chip has large features. Mind you if you have a SIMS unit that also can image (it is a modified SEM) so you might get away without duplicating eqt.

I'd recommend looking at PCB Design Guidelines For Reduced EMI by Texas Instruments.

While it is focused on reducing EMI, it offers advice or answers to all of your questions except "Manhattan Routing".

Section 2.1 (about 12 pages) is about Ground and power. It includes these useful sections:

2.1.7 Power Plane Do’s and Don’ts for Four-Layer Boards
2.2.1 Single-Point vs Multipoint Distribution
2.2.2 Star Distribution
2.2.3 Gridding to Create Planes

It shows how to get close to 4-layer PCB EMI performance using a 2-layer board. Part of reducing EMI is to ensure there is good power and ground routing and decoupling.