Some ARM cores like the ARM9 family of cores have a Harvard Architecture, at least at the cache level. That is they access two seperate caches, an I-cache for instructions and a D-cache for data ( example ARM926EJ-S ).
However the I & D caches wind up being interfaced to plain vanilla SDRAM externally. So it seems that at the RAM level we are back to the von Neumann design where one store ( SDRAM ) holds instructions >and< data.
In the example designs I've seen there seems to be just one single bus interfacing the SDRAM to the SOC chip.
How are the instructions and data differentiated, sorted and routed from the combined bus interfacing the external SDRAM to the internal I and D caches?
Best Answer
The control logic records why it issued a particular fetch to a particular address, so it can do something sensible with the result. There will be a small queue of outstanding fetches (remember, fetching from DRAM may take hundreds of cycles). On a value arriving, it's written back to the part of the architecture that requested it, and the relevant part of the processor's pipeline is un-stalled.