Electronic – SPI flash chip failing without a 1M resistor from power pin to ground

bypass-capacitorflashspi

Why would an SPI flash chip stop working after a short random period of time but work fine with a 1M resistor from the power pin to ground?

I'm debugging a problem with an SPI flash chip (W25Q80) driven by Atmega 328P at 765 KHz SPI clock stopping to work after random small intervals of time (200ms-5s) or not working right from the power up. This failure is seen as the chip stopping to respond on the MISO line (the line is floating) where it was responding to the same command just before that (the same power up cycle).

I've tried ceramic through hole capacitors of 100nF, 100pF and 15pF from power pin to ground and this doesn't help.

Then I connected a scope to the power pin of the flash chip and it started working.

Connecting a resistor of 1M from the power pin to ground also makes it work.

What could be an explanation here? Am I using wrong bypass capacitors with wrong ESR and the resistor acts as a small but sufficient bypass cap with high enough ESR?

This is reproducible with 2 chips so this makes it less likely that this is because of a faulty chip.

The datasheet for the flash chip doesn't give any recommendations about bypassing.

Best Answer

Some things to think about and investigate:

  1. Are you 100% sure that the SPI Flash chip VCC has a good solid connection to the power supply?
  2. Do you have the possibility that the part is actually being phantom powered up through the input protection diodes of the input control signals?
  3. Check to make sure that the SPI Flash chip has a good solid GND connection in common with the microcontroller and the power supply.
  4. Carefully check your design to see if you possibly have a potential silicon charge injection / latch-up condition caused by biased input pins to the FLASH part when the VCC of the chip is not yet applied.
  5. Check during active communications between the MCU and the SPI Flash Chip if there are significant negative overshoots on the signal edges that go more than about 0.5V below the GND level as measured at the chip. Significant negative spikes can also disrupt the chip operation.
Related Topic