I'm attempting to set up SPI communications on a breadboard between two PIC18LF2550 microcontrollers. I'm using a fairly slow clock of ~750kHz, waiting ~300us between bytes, and signal integrity on the scope looks good.
I'm using SPI mode 0,1 (i.e. with configuration bits on both the master and slave PICs set to CKP=0, CKE=0), with a slave select line. I have cleared the SMP bit on both master and slave (this is required for the slave), meaning that SDI is sampled in the middle of the data output time.
When I disconnect the slave entirely and loop back the master SDO into the master SDI, the communication works reliably. Furthermore, if I add a delay of 100ns or so (5% of the clock period) to either the clock or data lines, the connection is still reliable; this is expected, since the sampling is in the middle of the data output time. This, and the fact that all the lines (SDO/SDI/SCK/SS) match figure 19-3 of the datasheet (pg. 203) (with CKE=CKP=SMP=0) makes me think that the master is working correctly.
When the slave MCU is connected, the data sent from the slave to the master is always received reliably, but only about 50% of the bits sent from the master are received correctly at the slave. The incorrect data received are usually shifted one bit 'early', as though the slave is clocking the data at the very end of the clock period, and often reading data from the next bit instead. This hypothesis is supported by the fact that if the master SDO (slave SDI) line is delayed by a few nanoseconds, the data is 100% correct, whereas if the SCK line is delayed by a few ns instead, the data received is 100% incorrect.
Input sampling on the slave therefore seems to be occurring at the end of the data bit, but I would like it to occur in the middle of the data bit. However, the datasheet implies that, in slave mode, sampling can only occur in the middle of a data bit! (SMP must be cleared, as it is in my code). If I had set CKP or CKE wrongly, this might lead to sampling at the wrong time, but these are both set to 0 in both master and slave as required, and bits on the SDI/SDO lines are not half-a-bit out of sync, as might be expected if the clock polarity was set wrongly on one PIC.
Can anyone suggest what is going on?
Best Answer
As Sphero Pefhany notes, the list of silicon errata for the PIC18F2455/2550/4455/4550 family is extensive. In particular, erratum 37 (applicable to three revisions, including my revision B5 chips) reads
I assume the purpose of this resistor is to slow down the data transition, to make sampling at the end of the clock period (more) reliable.
This bug has been fixed in the latest (B7) revision.