Electronic – STM32f GPIO’s on 1.8V

gpiostm32stm32f4

So I'm trying to figure out what GPIO voltage levels on an STM32F4 would if I have my VDD at 1.8V. I'm assuming you just use the minimum values, however the conditions state 2.7V < Vdd < 3.6V, that means either the conditions were only tested for that voltage range OR they only hold for that range. There isn't any other info in the datasheet on Voh and 1.8V

In previous digital devices, I've seen differences between the different voltages (like 2.4v and 3.6V). So for 2.4V it would be Vdd-0.2 and for 3.3V it would be Vdd-0.4.

You can run this chip at 1.8V, that's stated elsewhere in the datasheet. Under table 6.3.1

VDD: Standard operating voltage 1.7V – 3.6V

What is my minimum Voh and max Vol range for CMOS on an I/O Pin if my Vdd is 1.8?

Best Answer

I'm trying to figure out what GPIO voltage levels on an STM32F4 would if I have my VDD at 1.8V.

What is my minimum Voh and max Vol range for CMOS on an I/O Pin if my Vdd is 1.8?

The table which you kindly included, might suggest that it was for a device which was only supported down to V_DD = 2 V (i.e. the lowest voltage mentioned in that table).

However the datasheet for the STM32F437 gives these V_OL and V_OH figures below, which specifically include V_DD = 1.8 V as you asked:

Related Solutions

Electronic – Stm32f discovery internal clock

OK I figured it out. There is a mistake in the STM32F4xx_spi.c Peripheral Driver file that doesn't allow the use of the HSI(internal clock) value needed for calculating the appropriate divider and odd values for the I2SPR register. (see the last line) I changed it to:

  i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr);

and now it works. Hours wasted as usual!! The clock configuration tool is also wrong as it creates a message in the system_stm32F4xx.c file that states

*        To achieve the following I2S config:   |
*         - Master clock output (MCKO): ON      |
*         - Frame wide                : 16bit   |
*         - Audio sampling freq (KHz) : 48      |
*         - Error %                   : 0.0186  |
*         - Prescaler Odd factor (ODD): 0       |
*         - Linear prescaler (DIV)    : 2       |

which conflicts with the programmers reference that ODD=1 and DIV=3 for 48kHz sample rate, which is correct.

/* Get the PLLI2SN value */
plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
                  (RCC_PLLI2SCFGR_PLLI2SN >> 6));

/* Get the PLLI2SR value */
pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
                  (RCC_PLLI2SCFGR_PLLI2SR >> 28));

/* Get the PLLM value */
pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);      

/* Get the I2S source clock value */
i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);

How does a stm32f chip set its GPIO speed? (hardware, not register setting)

Generally this is done by having multiple different drivers for the line, of different sizes and therefore with varying output impedance. Recall the basic CMOS driver:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Making the transistors larger increases their drive strength and lowers their on-resistance, but requires more charge to be moved on and off the gate when changing state. That results in increased power consumption.

Best Answer

Related Solutions

Electronic – Stm32f discovery internal clock

How does a stm32f chip set its GPIO speed? (hardware, not register setting)

Related Topic