How would one go about making a shift register which only shifts when an enable line is high? The obvious answer is to pass the clock and enable through an AND gate, but that breaks the "don't gate clocks" rule. Another possibility might be using a mux to select the input of each flip-flop to either be the previous flip-flop's output, or to feed its own output back to the input. That would work for the shift register, but is there a better way? How are similar effects achieved in complex designs, where portions of the functionality can be temporarily stopped to save power?
Electronic – Stopping the clock without gating the clock
clockdigital-logic
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That link you gave says it all:
Hint: - 2’s complement of a number can be obtained by keeping the least significant bits as such until the first 1, and then complementing all bits
"example 001010 → 110110" that is to say
001010 -> flip bits -> 110101 -> add 1 -> 110110
msb lsb msb lsb msb lsb
msb lsb
input 001010
output 110110
<--- time
So there are two states - "I haven't seen a one yet" and "I have seen a one previously". Given my state and my current input, my output and next state are fully determined.
If my current state is "I haven't seen a one yet" and my input is a 0, my output is a 0 and my next state is (still) "I haven't seen a one yet"
If my current state is "I haven't seen a one yet" and my input is a 1, my output is a 1 and my next state is (changes to) "I have seen a one previously"
If my current state is "I have seen a one previously" and my input is a 0, my output is a 1 and my next state is (still) "I have seen a one previously"
If my current state is "I have seen a one previously" and my input is a 1, my output is a 0 and my next state is (still) "I have seen a one previously"
Write that out as a truth table encoding "I haven't seen a one yet" as 0 and "I have seen a one previously" as 1, and you should be home free.
To "wire it up" the current data input bit and the current state go into logic that feeds the input to the D-flip flop and separate logic that feeds the input to the shift register, the D-flip-flop holds the "state variable", and both are clocked by the data clock. And to be complete you need some kind of reset logic - left as an exercise to the reader. The "current state" is the output of the D-flip-flop, and next state is the input to it...
+----------------------------+
| |
| +---------+ +-----+ |
+--+ Logic A +-----+ DFF +---+
Data-+-|--+ | | |
| | +---------+ | CLK |
| | +--+--+
| | |
| | +--------Clock
| | +--+--+
| | +---------+ | CLK |
| +--+ Logic B +-----+ |
+----+ | | S R |
+---------+ +-----+
The sophistication of your clock gating depends on how much the downstream logic is going to respond to a bad clock pulse.
For example: If the downstream logic is always reset after the clocks switch then you can get away with almost anything for your clock gating logic.
However, if you are expecting the downstream logic to continue functioning properly when the clocks are switched (without a reset) then you gating logic must be designed so that you never have clock pulses that are too short and violate your timing constraints.
The danger with short clock pulses that violate your timing constraints is that it could put a state machine into an invalid state that it can't recover from. This is really easy to do, so don't take it for granted that it won't happen to you.
Designing good clock gating/switching logic that doesn't produce short clock pulses is difficult and usually requires intimate knowledge of your ASIC process. Rather than invent your own, I suggest that you talk with your ASIC house or whoever you got your ASIC libraries from. Odds are very high that they already have the circuit you need.
Update:
The OP indicated that the clock gates in the schematics are from the ASIC library. If those gates are designed to not glitch (I.E., they never produce a pulse that is too short), then the only trick is to allow enough time between disabling one clock and enabling the next. In this way you can cleanly switch between clocks and not have clock glitches.
Designing the logic to do this (keep enough time between disable/enable) is still difficult, but not super difficult. On a scale of 1-10, this would be a 6. Designing a glitchless clock gate, on the other hand, would be a 10 or even 12!
Best Answer
Depends on the flip-flop used in the shift register. Effectively, negate the enable line or assert the disable line :-), but you know that.
I'd ask, "Why not gate clocks, provided that you gate them 'properly'?"
A hazard is that if you asynchronously gate a clock you may (~= 50% chance for a symmetric clock) produce an additional clock transition at disable or re-enable time. ie DO NOT DO THIS
BUT if you gate synchronously so that eg when gate off the clock continues to its next high/low transition, then stays low while still gated off, then when gated on resumes on the next clock low/high edge.
As described that may allow a very narrow spike at either edge if gating signal just precedes a clock low/ high transition but a bit of common sense in implementation stops that.
Effectively if delay is acceptable between provided and utilised clock signal (and usually one clock cycle is indistinguishable from the next) then having a toggling FF in the clock line and disabling it will implement the above (possibly with the described spike hazard present.)
In this circuit from - FPGA Design tips
They say
Partially answering my "why not" question above - the gated clock will be delayed by the toggle propogation delay of the gating flip-flop. In some cases this does not matter, in others it's clearly ubbacceptable. The 3rd, worst case, is where it seems OK but sometimes just may not be, on an intermittent basis. So, use with care.
On this page Roadie Roger warns
And Robert usefully counters
Depends on your target technology. The above may hold for FPGA's, but for standard-cell based ASIC technologies, gated clocks are an elegant (in my opinion) and clean methodology for low-power design.
In this case, you will most likely be using a clock tree generator anyway, and all of the clock tree generators I know easily handle clock gates. They will automatically align the clocks AFTER any possible gates, i.e. at the leaf nodes (clock inputs of registers). In this case, generating a low-skew clock tree is far easier for gated clocks than for derived clocks (i.e. divided clocks).
Modern synthesis tools also can insert clock gates automatically by replacing register enables (as shown in the post above) by gated clocks. This can be handy, but it has the drawback of reducing your control over clock gates (names, hierarchy).
Inserting clock gates in a VHDL design is easy. Just decide what gating style you want/need (and/or based, with/without latch, with test bypass, observability, ...).
My choice is to then explicitly instantiate a clock gating element where needed. This has the disadvantage of requiring one to "route" different clock signals through the design, but it gives you full control over clock gating elements for use in later stages of the design (clock tree generation, physical optimization, ...).
Information about "clean" clock gating can be found in books or also in synthesis tool manuals (where automatic clock gate insertion is described). Probably you'll also find resources on the web.