Electronic – Supply voltage in a current mirror necessary

If you use faster transistors and add a bit of bias you can reduce the delay significantly. For example:

^{simulate this circuit – Schematic created using CircuitLab}

This has simulated rise time of < 4ns.

We know that the condition for saturation is Vds >= Vgs - Vt or Vd >= Vg - Vt (1) or Vg <= Vd + Vt; So therefore the gate of M3 / M4 has a voltage of Vg3,4 = Vd_min + Vt (assuming Vk has the same dimension as the rest of the MOSFET).

Now coming to the gate of M1/M2. For this we would have to know the drain voltage of M3 because this is connected to M1. Let the voltage at drain of M3 = Vx since drain of M3 is connected to the gate of M1, according to (1) the drain of M1 = Vx- Vt. This means that only Vt can be dropped accross Vds3 to keep M1 in saturation. This makes M3 to act as if it is in a virtual diode connected fashion because Vg3= Vd3= Vd_min + Vt. This vt dropping accross M3 leaves V_dmin accross M1 sufficielntly putting it in saturation.

Now we know all the voltages of the MOSFET in the left side, since M3 M4 pair and M1 M2 pair are current mirrors the same current flows through them and therfore Vgs4= Vgs3. Since the Vg3,4 is fixed the source M3,4 should be at V_dmin. So V_dmin is dropped accross M2 to keep it in saturation as well. So now for the drain of M4 according to (1) to keep M4 alone in saturation Vd4 should at least be = Vg4-Vt = Vd_min. But to keep both M4 and M2 in saturation Vd4 should be at least = 2Vd_min. This improves the swing by a margin of Vt compared to a normal cascode structure which has a V_minimum of 2Vd_min + Vt.