Electronic – SystemVerilog: How to give different parameters to modules in the same array

system-verilogverilog

In my design, I wanted to use a number of counters with different initial values on reset. Therefore I defined the counter module as follows:

module my_counter #(parameter int INIT_VALUE = 0)
    (
        input clock, reset,
        ...

Then in the design I have 4 instances of mycounter that share a lot of inputs, but have different initial values. I'd like to make them a module array, but the best way I've come up with is:

defparam my_counters[0].INIT_VALUE = 0;
defparam my_counters[1].INIT_VALUE = 1;
defparam my_counters[2].INIT_VALUE = 2;
defparam my_counters[3].INIT_VALUE = 3;
my_counter my_counters[3:0](
    .clock(clock),
    ...

That works with simulation, but I've heard that defparam is considered poor form. Furthermore, when trying to synthesize my design, the synthesizer complains that Syntax error at or near token '['. on the lines with defparam.

How could I do what I wanted to do without a lot of code duplication?

Best Answer

Use a generate loop

for(genvar ii=0; ii<4; ii++) begin : counter_loop
  my_counter #(.INIT_VALUE(ii)) my_cnt (.clock, .reset ... );
end : counter_loop

If the values you want to override cannot be computed by a simple loop expression, you can use a parameter array.

parameter int ARRAY_VALUE[4] = {1,3,5,10};
for(genvar ii=0; ii<4; ii++) begin : counter_loop
    my_counter #(.INIT_VALUE(ARRAY_VALUE[ii])) my_cnt (.clock, .reset ... );
end : counter_loop

Related Solutions

Electronic – Generate gate with a parametrized number of inputs

If I understood your question correctly, I think the following module does what you want. You can very simply specify the gate by its operator (^,&,|, etc) and nothing else. Plus only the desired assignments are generated (which is I think what you are looking for).

`timescale 1 ns / 1 ps

module selectable_gate(input [7:0] in, output out);

parameter [7:0] SELECT = 8'b10010100;

function integer count_ones;
  input [7:0] v;
  integer ret;
  integer i;
  begin
    ret = 0;
    for(i=0;i<8;i=i+1) begin
      if (v[i]) begin
        ret = ret+1;
      end
    end
    count_ones = ret;
  end
endfunction

function integer nth_one;
  input integer n;
  input [7:0] v;
  integer i,ret,cnt;
  begin
    ret = -1;
    cnt = 0;
    for(i=0;i<8;i=i+1) begin
      if (v[i]) begin
        if (cnt == n) begin
          ret = i;
        end
        cnt = cnt+1;
      end
    end    
    nth_one = ret;
  end
endfunction

localparam integer w = count_ones(SELECT);
wire [w-1:0] y;

generate
  genvar i;
  for(i=0 ; i<w ; i=i+1) begin
    assign y[i] = in[nth_one(i,SELECT)];
  end
endgenerate

assign out = ^y; // specify gate here (e.g. ^y, &y, |y, etc)

endmodule;

The above module for the default SELECT = 8'b10010100 should end up generated as:

assign y[0] = in[2];
assign y[1] = in[4];
assign y[2] = in[7];
assign out  = ^y;

Which is the same as xor(in[2],in[4],in[7]).

Since genvars are always unrolled as constants inside the generates, the trick was to find constants that allow the proper conditions for the generate, and use functions for any temporary variable manipulation necessary to calculate them.

Electronic – Instantiating Parameterized Modules in SystemVerilog

change const to parameter

parameter int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37};
...
genvar n;
for (n = 0; n < 11; n++) begin : gen_loop
        PrimeCounter #(primeArray[n]) counter ( .match(match[n]), .* );
end

working example here

I added initial $display("%m id:%0d",id); into my PrimeCounter, output is as follows:

# dut.gen_loop[0].counter id:3
# dut.gen_loop[1].counter id:5
# dut.gen_loop[2].counter id:7
# dut.gen_loop[3].counter id:11
# dut.gen_loop[4].counter id:13
# dut.gen_loop[5].counter id:17
# dut.gen_loop[6].counter id:19
# dut.gen_loop[7].counter id:23
# dut.gen_loop[8].counter id:29
# dut.gen_loop[9].counter id:31
# dut.gen_loop[10].counter id:37

Best Answer

Related Solutions

Electronic – Generate gate with a parametrized number of inputs

Electronic – Instantiating Parameterized Modules in SystemVerilog

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