Electronic – systemverilog structure initialization with default = ‘1

hdlsystem-verilogvivado

Can someone shed light on what this SystemVerilog code should do:

typedef struct {
 logic [15:0] a;
 logic [15:0] b;
 logic [15:0] c;
} my_struct;

localparam my_struct s = '{default:'1, c:0};

Is this legal? I can't quite figure out the spec well enough to tell. This doesn't work right with Vivado, and I'm not sure why.

This works:

localparam my_struct s = '{default:0, c:'1};

Thanks,
Nachum

Best Answer

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns

my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000};
my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF};

Your version Vivado might not have implemented the default:'1 feature yet or it could be a bug in the simulator. Try to run the latest version.

Try default:16'hFFFF or default:-1 as possible work around.

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