Here's an overview of the design process to get you started. I'll let you work out the exact calculations.
I would replace \$R_{\text{load}}\$ with an independent current source \$I_{\text{load}}\$ for your simulation (you can use your CircuitLab schematic for simulation once you add resistor values). Set \$I_{\text{load}} = 25\$mA since that is your worst case.
Pick a relatively large emitter resistor \$R_3\$. This simply provides a load to the transistor if the actual load isn't connected (e.g. \$I_{\text{load}} = 0\$). For example, use \$R_3 = 10\$k\$\Omega\$. If \$V_{\text{out}} = 5\$V then the current through \$R_3\$ is \$0.5\$mA and \$I_{E} \approx 25.5\$mA in the worst case (\$I_{\text{load}} = 25\$mA).
Next you need to determine the worst case (highest) \$I_B\$. Use the lowest \$\beta\$ in the transistor's datasheet (worst case) and then calculate
$$I_B = \frac{I_E}{\beta + 1}$$
Now in order to make the resistor voltage divider "stiff" you need to make sure that the unloaded bias current through the resistors (call it \$I_{\text{div}}\$) is at least 10 times the load current (in this case \$I_B\$ is the load for the voltage divider). Otherwise the load current draws too much current away from \$R_{2}\$, which causes the voltage at the output of the voltage divider decrease too much. This puts a constraint on the maximum value of \$R_1 + R_2\$ since
$$I_{\text{div}} = \frac{15}{R_1 + R_2} > 10I_B$$
This equation plus the voltage divider equation
$$\frac{R_2}{R_1+R_2}15 = 5.6$$
gives you two equations and two unknowns.
The book's approach is an estimation, on the assumption that the base current is negligible - which turns out to be not so great of an assumption here, as you found out.
your approach is more precise, but made the same mistake right here:
The maximum current through the divider without connected load is:
Idiv=VccR1+R2=15280⋅103≈54μA
you didn't factor in the equivalent resistance on the base side: at 8.1v @ 10ua, that's equivalent to a 810K resistor (approximately Re * beta - see note below).
So the lower resistor R2 is paralleled by a 810K resistor. Once you factor that in your calculation, it will be alright.
Most people don't take that approach. for example, I typically set the current through R1/R2 to be 10x of the base current. That yielded R1 + R2 = 15v / 100ua = 150K. and go from there for R1/R2 individually. the 10x is picked to make sure that the base current is indeed negligible.
what it shows you is that 1) don't put too much stock in any book; and 2) don't take estimation too seriously. many times, good enough is indeed good enough.
edit:
note: for better approximation, some people would assume that the lower resistor is by-passed by a equivalent resistance of beta * Re -> 750K in this case, vs. 810K the real one calculated earlier. This approach works fairly well as an approximation.
Best Answer
One major parameter which decide biasing in BJT transistors is Bias Stability. As β (hFE) widely varies from transistor to transistor. An stable biasing will provide minimum alteration in the Q-point on wide changes in β.
Mathematically stability factor is denoted by,
S= delta Ic / delta Icb.
S depends on the circuit configuration and the bias resistors. S should be as small as possible.
Consider the thress biasing,
Now you can choose a biasing with low value of 'S' for better stability.
We never desire high value of 'S'. If one of the transistor stop working in your design then it's replacemnt may not have the same Beta. You want least effect on the Q-point due to the error in beta value. So need a low value of 'S'.
Consider these calculations:
VCEQ changes by 41% when β changes by 50%.
VCEQ changes by 25% when β changes by 50%.
VCEQ changes by 6% when β changes by 50%.