Electronic – The concept of DDR rank

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I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity.

Here is what I know

  1. A DDR rank is a 64bit interface consisting of x8 or x16 devices
  2. Each rank is controlled by an individual CS. So two ranks means 2 CS signals to control them
  3. A CA bus is shared among devices of different ranks. Two devices in the same rank don't share the CA bus.
    All of the confusion started when I saw the following images based on which I have few questions
    Single Rank

In the above image as the CA bus is not shared, both the devices are on the same rank.

  1. So does that mean external to the package the CS pins have to be shorted i.e CS0_A and CS0_B should be controlled by 1 CS pin from the controller?
  2. If we keep the CS pins separate and don't short them, doesn't that make the operation dual rank?
  3. Is an x32 bit interface from a package enough to constitute a rank?

Dual rank

Here is a dual-rank package from which I concluded that CA buses must be shared among devices of different ranks.

  1. So in the dual-rank package should we have only 2 bit CS to control the two ranks or can we have a separate CS control for each device in the 2 rank config?

The rank concept is highly confusing hence the questions.

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