Is it possible at all?
Well, maybe yes.
Is it feasible to do this on commercially produced motherboards with
soldered RAM chips found on consumer electronic devices?
Definitely no. Connecting wires to the lines between the CPU and the RAM without disturbing communications is extremely difficult. The faster the bus is, the more difficult this is. Replacing the RAM chips with something (a larger FPGA + external RAM would probably suffice) that "simulates" a RAM chip to the modified system and does whatever you want with the data is probably a lot more feasible.
Are there any off-the-shelf devices that can do this?
Most probably no.
This is my understanding:
In http://www.freescale.com/files/32bit/doc/app_note/AN2826.pdf, it recommends to put the series termination at the processor side, because the the memory side, it recommends a parallel termination resistor too. So, both end are terminated.
And assume we only terminate at one end. According to Micron's: Termination for Point-to-Point Systems:
If only one end of a transmission line is matched, signals will
reflect off the unmatched end and then terminate into the matched end.
The configuration in which the driving impedance is matched and the
receiving end is not is known as back terminating (see Figure 10 on
page 5). Signals that come from the source travel down the
transmission line, reflect off the unterminated end, then travel back
through the transmission line and terminate in the source resistor.
Although there is a reflection, this reflection does not distort the
signal at the receiving end.
It's the reflected signal will make the things worse, so when the signal goes to receiver (DDR) then reflected back, if we terminated at source end, then there will no further reflected signal to receiver, so the receiver won't be distorted, the source may be distorted.
That is the case for one source and one receiver, unidirectional connection. Then what about bidirectional connection? Some materials suggest to terminate at middle, such as Freescale's: Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces:
If series damping (RS) terminators are used (not seen as mainstream
approach), were they placed close to the first memory DIMM?
For discrete implementations—Placement of the series damping resistor
(RS) for the data group is left to the board designer. This trade-off
is optimal signal integrity for both reads/writes (RS in middle)
versus ease of layout routing (RS placed closer to memory devices).
These all are some "recommendations", the safer method maybe do some simulations with HyperLynx or other tools to judge the best termination method and termination position.
Best Answer