I know that beyond a threshold voltage VGS, increasing the gate-source voltage VGS in a field-effect transistor (FET) increases the drain-source current IDS quadratically. I've looked on the web and in textbooks, and I don't see any explanation for what limits the quadratic growth.
Assuming that I have plenty of source-drain voltage VDS, what is the limiting behavior for very large gate-source voltages VGS in a FET?
Some thoughts:
- Increasing VGS continues to open up the channel, and the resistance continues to decrease, causing quadratic growth in the current indefinitely until either the device burns up and you reach for the fire extinguisher, or the extreme electric field causes a breakdown between the gate and the channel. See dashed line in attached figure.
- Increasing VGS beyond a certain point gives diminishing returns. The maximum current is limited by some (??) physical effect (e.g., maximum electron velocity in the semiconductor). See dotted line in the figure.
Does anyone have any good references for this? Is the behavior drastically different between MOSFETs, JFETs, MESFETs, HEMTs, and other transistors?
Hand wavy explanation < Physical intuition < Physical intuition with mathematics (scientific papers / references preferred).
Best Answer
I think what you're looking for is an understanding of what drives the saturation current of a FET channel. There are various models for this (e.g. short vs long gates, high vs low Vth).
To first order it's electron concentration in the channel and electron drift velocity.
Isat = q * (Ns) * (vs) * W Ns is number of carriers, vs is saturation velocity.
To second order ohmic contact resistance and other parasitics factor in.
There is some more detailed insight in this (darn interesting, I wish there were an accompanying video!) course presentation: www.ee.sc.edu/personal/faculty/simin/ELCT563/19%20JFETs%20MESFETs%20HFETs.pdf