I am writing an FPGA driver in Verilog for a temperature sensor (datasheet available here). The communication protocol is SMBus, a close cousin of I2C. Now reading the datasheet, I understand that the ACK signal is composed of two parts (see page 10, figure 5):
- First, SDA is driven low on the 9th clock cycle
- Then, SDA is "spiked" (driven high, then immediately driven low) between the 9th and 1st clock cycles
This seems to contradict this tutorial where it is claimed that an ACK is simply done by driving SDA low (no "spike" is mentioned).
Is this "spike" actually included in the ACK signal? If so, how should I detect the "spike"?