dac
In the diagram shown bellow we have 1.5 bit ADC stage. We have Vin which is an analog signal and it could be translated as 00, 01, or 10.
In one bit we have only the option of 0 or 1. I can't see how it fixed an error, it's just dividing the range to more logical sections. I can't see any error fixing in here.
Is there simple practical example I could use to visualize how it happens?
You have two levels of DAC decoding the two most significant groups of 4 bits; for each the output is built summing the current from the sources according to the binary decoded value of the 4 bits:
15 sources, because the value 0000 means that no source is giving current;
Considering the output, 10.... is equal to 01.... but the fact is that you have the current sources active depending upon the input bits (see no. 1): if you have 0100, you'll have 4 current sources active;
binary weighted DAC is an architecture in which you use resistors with power of 2 values (you can use also switched capacitors or others); you have an op-amp where a reference voltage is feeded through these binary weighted resistors, that are switched accordingly to the input code.
To give a basic example of how a 1-bit ADC can be used to obtain useful information from a waveform, take a look at this circuit. It uses a triangle wave to turn the information into a pulse width modulated output. This is a similar but simplified version of how other 1-bit ADC techniques work, by using a (usually fedback) reference signal to compare the input to.
Circuit
Simulation
Magnified Timescale View:
We can see from the top input waveform, the triangle wave is used to compare the waveform at different points through it's period. As long as the triangle wave is of a considerably higher frequency than the input (the higher the frequency the more accurate), this causes the comparator to output an average of high/low depending on the voltage level of the waveform.
To see how we can reproduce the original waveform from the PWM data, the comparator output is fed into a low pass filter, and out pops the sine wave again.
For further reading:
Delta-Sigma Converters
Successive Approximation ADC
Single Bit ADCs
Ramp Compare ADC (Counter ADC)
Best Answer
Your figure shows one stage of a pipelined ADC.
The "error correction" is not an analog operation, but rather a digital operation that resolves any contradictions among the outputs of the stages. It is a correction of the error of thresholds applied in the ADC.
It is not the thresholds that are then corrected, but the digital output of the ADC stages are digitally recalculated based on redundancy among them, effectively overcoming the threshold errors.
This "error" is not to be confused with the "residual" or "quantization error" after each stage.
Conceptually, if there are 7 1-bit stages without any overlap or redundancy, there would be a 7 bit output.
When assembling a 7 bit value from the digital output of 7 stages with overlap (14 bits total), there is some redundancy to contend with, since each stage produces 1.5 bits of overlapping resolution, and 2 bits of code.
Each 1.5 bit stage has one of three values: Digital Output (-1 , 0, or +1), coded by two bits (using 3 of 4 permutations).
That "0" is tentative and will be resolved by the next stage, of which its output (again one of +1,-1,0) will be used by the "digital error correction" to resolve the uncertainty.
Here is a table, from the linked page below:
As an aside, the purpose of introducing the redundancy has to do with the accuracy of placing ADC comparator thresholds and the DAC output for residual subtractors. Clearly there should be no discrepancy between the decision threshold and the generated reference for the residual.
More:
https://www.maximintegrated.com/en/design/technical-documents/tutorials/1/1023.html
and
https://www.electronicdesign.com/technologies/analog/article/21775949/15bit-stages-in-pipeline-adcs (but figures are missing)
For an example, see my answer in visualising redundancy in1.5bit pipe line ADC