Simply put, a multiplexer selects one of its inputs and routes it through to the output.
S1 and S0 can be combined to create a 2-bit binary number. That number, when converted to decimal, corresponds to one of the 4 inputs, and that is the input that is then routed through to the output. For instance, if you have S1 = 1 and S0 = 0, that is the binary number 102, which is 210. So input 2 would be routed to the output.
The general truth table looks like this:
S1 | S0 | I0 | I1 | I2 | I3 || Out
----------------------------------
0 | 0 | X | X | X | X || I0
0 | 1 | X | X | X | X || I1
1 | 0 | X | X | X | X || I2
1 | 1 | X | X | X | X || I3
The "X" means "Don't Care", or more strictly "This value doesn't affect the results of the truth table". The output value as "I0" etc indicates that "The output is whatever this input is set to".
Taking your multiplexer from above, with a specific (fixed) set of values on the input pins (1, 0, 0, 1), the full expanded truth table would look like this:
S1 | S0 | I0 | I1 | I2 | I3 || Out
----------------------------------
0 | 0 | 1 | 0 | 0 | 1 || 1
0 | 1 | 1 | 0 | 0 | 1 || 0
1 | 0 | 1 | 0 | 0 | 1 || 0
1 | 1 | 1 | 0 | 0 | 1 || 1
If you were to take S1 and S0 as the inputs to some unknown logic gate, and examine the output from it to determine what the gate was, so ignoring the I0-I1 pins since they are fixed, you can equate that table to another known truth table. Let's collapse it by removing the static input values:
S1 | S0 || Out
--------------
0 | 0 || 1
0 | 1 || 0
1 | 0 || 0
1 | 1 || 1
The output is high when both the inputs are low or both the inputs are high, and the output is low when one and only one of the inputs is high and the other one is low. That sounds familiar to me. That sounds like the XNOR gate to me (an inverted XOR gate).
Of course, change the combination of values on the input pins, and you can change the way the output works. Just by inverting the whole of the inputs, so you have 0, 1, 1, 0 instead, will completely invert the output values, so the XNOR becomes an XOR. A different combination could make it look like an AND gate, or an OR gate, etc.
In this mode, where it is able to emulate any single low-level gate, is known as a "look-up table" where, instead of actually performing a logic function, it uses values to "look up" another value from another place, in this case the input pins.
Look-up tables are used extensively in FPGAs and other similar programmable logic, where the output of a logic cell can be, to a large extent, pre-programmed into a block of memory, and the incoming values just look up the output value in that memory. Just like a very large multiplexer.
The solution is very straight forward if you start by writing down a truth table. In the 16 count there are two sets of 8 corresponding to BC values (00,01,10, and 11). Pull these values out into their own truth tables and you see an interesting pattern for the values of A and D.
The value (BC) 00 corresponds to NOT A
The value (BC) 01 corresponds to D
The value (BC) 10 corresponds to NOT D
The value (BC) 11 corresponds to HIGH
Best Answer
The less efficient (and maybe more obvious) way is to connect fixed logic levels to each input of the multiplexer. You need a 2^N input multiplexer for N inputs. So, an 16-input mux for any function of 4 bits.
If, instead, you connect the respective inputs to either one of the inputs (that doesn't go to the multiplexer select input) or its complement, as required for the function, then you can halve the multiplexer size. So an 8-input mux (plus an inverter) for any function of 4 bits.